Module 2

8051 Architecture

2.1 8051 internal block diagram

8051 microcontrollers were designed by Intel in 1981. It is an 8-bit microcontroller. It is built with 40 pins DIP (dual inline package), 4kb of ROM storage and 128 bytes of RAM storage, 2 16-bit timers. It consists of four parallel 8-bit ports, which are programmable as well as addressable as per the requirement.

The reasons for the popularity of 8051 Microcontroller are –

2.2 CPU

The CPU acts as a mind of any processing machine. It synchronizes and manages all processes that are carried out in microcontrollers. The user has no power to control the functioning of the CPU. It interprets the program stored in ROM and carries out from storage and then performs it projected duty. CPUs manage the different types of registers available in 8051 microcontrollers.

It is the heart of the Microcontroller that mainly comprises an Arithmetic Logic Unit (ALU) and a Control Unit (CU) and other important components. The CPU is the primary device in communicating with peripheral devices like Memory, Input and Output.

2.3 ALU

ALU performs all arithmetic and logical functions.

Addition, subtraction with carry, and multiplication are categorized as arithmetic operations.
Logical AND, OR and exclusive OR (XOR) as logical operations.

2.4 Address, Data Bus and Control Bus

A bus consists of a group of wires to transfer data from one location to another within the system. Buses reduce the number of paths or cables needed to set up connection between components.

There are two kinds of buses - Data Bus and Address Bus

Data Bus: The purpose of a data bus is to transfer data. It acts as a channel for data to travel.

Address Bus: The purpose of address bus is to transfer information but not data. The information tells from where within the components, the data should be sent to or received from.

Control bus - carries control signals from the processor to other components. The control bus also carries the clock's pulses. The control bus is unidirectional

2.5 Working Registers

Registers are known as data storage devices. There are two registers namely Register A and Register B. Register A is used as an accumulator and Register B as general -purpose register. The output of mathematical and logical instructions are stored in these registers.
The operations of addition, subtraction, multiplication and division are performed by   Register A. Register B is for  multiplication and division which are carried by Register A. For data transfers between microcontroller and external memory Register A is involved.
 

8051 has four Register banks.

When the 8051 is first booted up Register bank 0 (addresses 00h through 07h) is used by default.

The internal memory supports 4 register banks.

The first 8 bytes (00h – 07h) are “register bank 0”.

Followed by Bank1 (08 – 0F),

Bank2 (10 – 17),

Bank3 (18 – 1F).

Register banks reside in the first 32 bytes of Internal RAM.
 

PSW (PROGRAM STATUS WORD)

This is an 8-BIT register. The Program Status Word (PSW) contains status bits that reflect the current CPU state. 

A (ACCUMULATOR)

Accumulator is an 8-bit register.It holds the result of most arithmetic and logic operations. This register is usually accessed by direct addressing. It is both byte and bit addressable.

B (EXTENSION REGISTER)

The major purpose of the B(Extension register) register is executing multiplication and division. This register is directly accessed when we are writing our code in assembly language. The 8051 microcontroller has a single instruction for multiplication (MUL) and division (DIV).    

SP (STACK POINTER)

Stack pointer is an 8- bit register, the direct address of SP is 81H and it is only byte addressable that means individual bits of stack pointer cannot be accessed. The content of the stack pointer points to the last stored location of the system stack. T

To store something new in the system stack, the SP must be incremented by 1 first and then execute the “store” command.

Push increments the SP and writes data.

DPTR (DATA POINTER REGISTER)

This is a 16 bit register. It is used to access external code or data memory
 The Data Pointer (DPTR) is the 8051’s only user-accessible 16-bit (2-byte) register.

2.6 SFRs

8051 microcontrollers also have 7 Special Function Registers (SFRs). They are:
1. Serial Port Data Buffer (SBUF)
2. Timer/Counter Control (TCON)
3. Timer/Counter Mode Control (TMOD)
4. Serial Port Control (SCON)
5. Power Control (PCON)
6. Interrupt Priority (IP)
7. Interrupt Enable Control (IE)
 

1. SBUF(Serial Buffer Register)

This is a serial buffer register which is used to transmit or receive data through it.

For holding data SBUF (Serial Port Data Buffer) register;

Manage data communication SCON (Serial Control) register

Managing data transfer rate PCON (Power Control) register

RXD and TXD establish serial networks.
 

SBUF register has 2 parts

For storing the data to be transmitted use TXD pin

For receiving data from other sources use an RXD pin.

Serial data communication operates in four modes. They are serial data
1. Mode 0 (shift register mode)
2. Mode 1 (standard UART)
3. Mode 2 (multiprocessor mode)
4. Mode 3

2. TCON Register

TCON is another register used to control operations of counters and timers in microcontrollers. It is an 8-bit register wherein four upper bits are responsible for timers and counters and lower bits are responsible for interrupts.

3.Timer/Counter Mode Control (TMOD)

4. Serial Port Control (SCON)

5. Power Control (PCON)

PCON Register: Power control register

PCON (Power Control) register is used to force the 8051 microcontrollers into power-saving mode. The power control register of 8051 contains two power-saving mode bits and one serial baud rate control bit.

Bit 7 – SMOD

1 = Baud rate is doubled in UART mode 1, 2 and 3.

0 = No effect on Baud rate.

Bit 3:2 – GF1 & GF0:

These are general purpose bits for users.

Bit 1 – PD: Power Down

1 = Enable Power-Down mode. In this mode, the Oscillator clock turned OFF and both CPU and peripherals stopped. Hardware reset can cancel this mode.

0 = Disable Power-down mode.

Bit 0 – IDL: Idle

1 = Enable Idle mode. CPU clock turned off whereas internal peripheral modules such as a timer, serial port, interrupts worked normally. Interrupt and H/W reset can cancel this mode.

0 = Disable Idle mode.

6. Interrupt Priority (IP)

We can change the priority levels of the interrupts by changing the corresponding bit in the Interrupt Priority (IP) register as shown in the following figure.

●        A low priority interrupt can only be interrupted by the high priority interrupt, but not interrupted by another low priority interrupt.

●        If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served.

●        If the requests of the same priority levels are received simultaneously, then the internal polling sequence determines which request is to be serviced.

7. Interrupt Enable Control (IE)

This register is responsible for enabling and disabling the interrupt. EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their meanings are shown in the following figure.

EA IE.7 It disables all interrupts. When EA = 0 no interrupt will be acknowledged and EA = 1 enables the interrupt individually.

- IE.6 Reserved for future use.

- IE.5 Reserved for future use.

ES IE.4 Enables/disables serial port interrupt.

ET1 IE.3 Enables/disables timer1 overflow interrupt.

EX1 IE.2 Enables/disables external interrupt1.

ET0 IE.1 Enables/disables timer0 overflow interrupt.

EX0 IE.0 Enables/disables external interrupt0.

2.7 Clock and RESET circuits

RESET is an active High input. When RESET is set to High, 8051 goes back to the power on state. The 8051 is reset by holding RST high for at least two machine cycles and then returning it low.

There are two method of reset circuit: 

1.Power On Reset.

2.Manual Reset

(1)  – Power on Reset

(2)  Manual Reset

Clock Circuit:

In general cases, a quartz crystal is used to make the clock circuit. The connection is shown in figure (a).  In cases of external clock sources the clock frequency limits (maximum and minimum) may change from device to device.

Standard practice is to use 12MHz frequency. If serial communications are involved then its best to use 11.0592 MHz frequency.

2.8 Stack and Stack Pointer

The stack is a section of RAM used by the CPU to store information such as data or memory address on a temporary basis. The CPU needs this storage area considering the limited number of registers.

As the stack is a section of a RAM, there are registers inside the CPU to point to it. The register used to access the stack is known as the stack pointer register.

The stack pointer in the 8051 is 8-bits wide, and it can take a value of 00 to FFH. When the 8051 is initialized, the SP register contains the value 07H. This means that the RAM location 08 is the first location used for the stack.

The storing operation of a CPU register in the stack is known as a PUSH, and getting the contents from the stack back into a CPU register is called a POP.

Pushing into the Stack

In the 8051, the stack pointer (SP) points to the last used location of the stack. When data is pushed onto the stack, the stack pointer (SP) is incremented by 1. When PUSH is executed, the contents of the register are saved on the stack and SP is incremented by 1. To push the registers onto the stack, we must use their RAM addresses.

For example, the instruction "PUSH 1" pushes register R1 onto the stack.

Popping from the Stack

Popping the contents of the stack back into a given register is the opposite to the process of pushing. With every pop operation, the top byte of the stack is copied to the register specified by the instruction and the stack pointer is decremented once.

2.9 Program Counter

The program counter points to the address of the next instruction to be executed. As the central processing unit [CPU] fetches the opcode from the program ROM, the program counter is incremented to point to the next instruction.

The program counter in the 8051 is 16-bits wide. This means that the 8051 can access program addresses 0000 to FFFFH, a total of 64K bytes of code.

Consider the action of the program counter as fetching and executing a program. First, we examine the list file of the sample program taken from the previous section-IIIa and see how the code is placed in the ROM of an 8051 chip.

2.10 I/O ports

8051 microcontrollers have 4 I/O ports each of 8-bits configured as input or output. Hence, total 32 input/output pins allow the microcontroller to be connected with the peripheral devices.

●        Pin configuration, that is the pin is configured as 1 for input and 0 for output as per the logic state.

• Input/Output (I/O) pin − All the circuits within the microcontroller must be connected to one of its pins except P0 port because it does not have pull-up resistors built-in.
• Input pin − Logic 1 is applied to a bit of the P register. The output FE transistor is turned off and the other pin remains connected to the power supply voltage over a pull-up resistor of high resistance.

●        Port 0 − The P0 (zero) port is characterized by two functions −

• When the external memory is used then the lower address byte (addresses A0A7) is applied on it, else all bits of this port are configured as input/output.
• When P0 port is configured as an output then other ports consisting of pins with built-in pull-up resistor connected by its end to 5V power supply, the pins of this port have this resistor left out.

Input Configuration

If any pin of this port is configured as an input, then it acts as  “floats” , that is the input has unlimited input resistance and in-determined potential.

Output Configuration

When the pin is configured as an output, then it acts as an “open drain”. By applying logic 0 to a port bit then appropriate pin will be connected to ground (0V), and applying logic 1, the external output will keep on “floating”.

To apply logic 1 (5V) on this output pin, it is necessary to build an external pullup resistor.

Port 1

P1 is a true I/O port as it does not have any alternative functions as in P0, but this port can be configured as general I/O only. It has a built-in pull-up resistor and is completely compatible with TTL circuits.

Port 2

P2 similar to P0 when the external memory is used. Pins of this port occupy addresses intended for the external memory chip. This port can be used for higher address byte with addresses A8-A15. When no memory is added then this port can be used as a general input/output port similar to Port 1.

Port 3

In this port, functions are similar to other ports except that the logic 1 must be applied to the appropriate bit of the P3 register.

2.11 Memory Structures

8051 Memory Organization

The 8051 Microcontroller Memory is separated into Program Memory (ROM) and Data Memory (RAM). The Program Memory of the 8051 Microcontroller is used for storing the program to be executed, which means instructions. The Data Memory is used for storing temporary variable data and intermediate results.

Program Memory (ROM) of 8051

The code or instructions which are to be executed are stored in the Program Memory, also called as the ROM of the Microcontroller.

Program Memory

In 4KB Internal ROM, the address space is 0000H to 0FFFH. If the program addresses exceed this value,the CPU will automatically fetch the code from the external Program Memory.

For  External Access (EA Pin) must be pulled HIGH at this condition the CPU first fetches instructions from the Internal Program Memory in the address range of 0000H to 0FFFFH .If it exceeds the memory addresses limit, instructions are fetched from external ROM in address range of 1000H to FFFFH.

External access

There is also an alternative method to fetch the instructions where the Internal ROM is ignored and instructions are fetched only from External Program Memory(External ROM).

For this purpose, the EA pin must be connected to GND. The memory addresses of external ROM will be from 0000H to FFFFH.

External Program Memory

Data Memory (RAM)

Lower 128B(00H to 07H) Upper 128B(80H-FFH)

(Direct and Indirect Addressing)   (Direct Addressing)    (Indirect Addressing)

2.12 Timing diagrams and Execution Cycles

The processor decodes the instruction in the instruction register and generates the necessary control signals to execute the instruction. Based on the instruction further operations such as fetching, writing into memory etc takes place.

Timing diagram for op-code fetch cycle.

Memory Read Machine Cycle:

The memory read cycle is executed by the processor to read a data byte from memory.

The machine cycle is exactly same to opcode fetch except:

a) It has three T-states

b) The S0 signal is set to 0.

The timing diagram of this cycle is given in

Timing diagram for memory read machine cycle.

Memory Write Machine Cycle:

The memory write cycle is executed by the processor to write a data byte in a memory location. The processor takes three T-states and ^(WR) signal is made low. The timing diagram of this cycle is given in Figure.

I/O Read Cycle:

The I/O read cycle is executed by the processor to read a data byte from I/O port or from peripheral, which is I/O mapped in the system. The 8-bit port address is placed both in the lower and higher order address bus. The processor takes three T-states to execute this machine cycle. The timing diagram of this cycle is given in Figure

I/O read machine cycle

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