3.1 Sequential circuits | unit 3 synchronous sequential logic design

DSD

Unit - 3

Synchronous Sequential logic Design

3.1 Sequential circuits

A Sequential circuit consists of inputs variable (X), logic gates and output variable (Z).

Combinational circuit generates an output on the basis of input variable only but Sequential circuit produces an output based on current input and previous output variables.

This means that it includes memory elements which are capable of storing binary information.

This binary information is nothing but the state of the sequential circuit at any given time. A latch capable of storing one bit information.

Fig. 1 Combinational circuit

Fig. 2 Sequential circuit

There are two types of input to the combinational logic in fig 2:

External inputs which are not controlled by the circuit.

Internal inputs which are function of previous output states.

Secondary inputs are state variables that are produced by the storage elements whereas secondary outputs are excitations for those storage elements.

Types of Sequential Circuits –

There are two types of sequential circuit:

Asynchronous sequential circuit –

They do not use a clock signal but instead uses the pulses as inputs.

These circuits are faster because there is clock pulse and can change their state immediately when there is a change in the input signal.

It is used when speed of operation is important and is independent of internal clock pulse.

Fig. 3 Asynchronous Sequential circuit

But they are more difficult to design and their output is also uncertain.

Synchronous sequential circuit –

These circuit uses clock signal and level inputs.

The output pulse is received in the same duration as the clock pulse for the clocked sequential circuits.

They wait for the next clock pulse to arrive to perform the next operation, these circuits are bit slower as compared to asynchronous circuits.

Level output changes state at the start of an input pulse and remains in that state until the next input or clock pulse arrives.

Fig. 4 Synchronous Sequential circuit

It is used in synchronous counters, flip flops, and in MOORE-MEALY machines.

It is also used to design Counters, Registers, RAM, etc

Key takeaway

Asynchronous sequential circuit –

They do not use a clock signal but instead uses the pulses as inputs.

These circuits are faster because there is clock pulse and can change their state immediately when there is a change in the input signal.

Synchronous sequential circuit –

These circuit uses clock signal and level inputs.

The output pulse is received in the same duration as the clock pulse for the clocked sequential circuits.

3.2 Storage elements: Latches (SR, D)

Latches are basic storage elements that operate with signal levels (rather than signal transitions). Latches controlled by a clock transition are flip-flops. Latches are edge-sensitive devices. Latches are useful for the design of the asynchronous sequential circuit.

SR (Set-Reset) Latch –

SR Latch is a circuit which has:

(i) 2 cross-coupled NOR gate or NAND gate.

(ii) 2 input S for SET and R for RESET.

(iii) 2 output Q and Q’.

Q	Q’	STATE
1	0	Set
0	1	Reset

Under normal conditions, both the input remains 0.

RS Latch with NAND gates:

Case-1: When S’=R’=1 or S=R=0 then

If Q = 1, Q = R’ = 1.

If Q = 0, Q = 0 and R’ = 1 respectively.

Case-2: S’=0, R’=1 (S=1, R=0)

As S’=0, Q = 1(SET state).

In 2nd NAND gate, as Q = R’ = 1, Q’=0.

Case-3: S’= 1, R’= 0 (S=0, R=1)

As R’=0, Q’ = 1.

In 1st NAND gate, as Q =S’ = 1, Q=0 (RESET state).

Case-4: S’= R’= 0 (S=R=1)

When S=R=1, both Q = Q’ = 1 which is not allowed.

So, this input condition is prohibited.

The SR Latch using NOR gate is:

Gated SR Latch –

It is a latch which enable input that works when enable = 1 and retain the previous state when enable = 0.

Gated D Latch –

It is similar to SR latch with little modifications. Here, the inputs are complements of one another. The design of D latch with Enable signal is given below:

The truth table is shown below:

ENABLE	D	Q(N)	Q(N+1)	STATE
1	0	x	0	RESET
1	1	x	1	SET
0	x	x	Q(n)	No Change

As the output is same as input, it is also known as Transparent Latch.

The characteristic equation for D latch with enables input is given as:

Q(n+1) = EN. D + EN’. Q(n)

Key takeaway

Latches are basic storage elements that operate with signal levels (rather than signal transitions). Latches controlled by a clock transition are flip-flops. Latches are edge-sensitive devices.

3.3 Storage elements: Flip-flop’s inclusion of Master-Slave

RS Flip Flop

JK Flip Flop

D Flip Flop

T Flip Flop

Logic diagrams and truth tables of the various types of flip-flops are as follows:

S-R Flip Flop:

J-K Flip Flop:

D Flip Flop:

T Flip Flop:

Race Around Condition in JK Flip-flop –

For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then output Q will toggle as long as CLK remains high which makes the output unstable or uncertain.

This problem is known as race around condition in J-K flip-flop.

This problem can be avoided by ensuring that the clock input is at logic “1” only for a very short time.

Hence the concept of Master Slave JK flip flop was introduced.

Master Slave JK flip flop –

It is basically a combination of two JK flip-flops connected together in series.

The first is the “master” and the other is a “slave”.

The output from the master is connected to the two inputs of the slave whose output is fed back to inputs of the master.

In addition to these two flip-flops, the circuit comprises of an inverter.

The inverter is connected to clock pulse in such a way that an inverted clock pulse is given to the slave flip-flop.

In other words, if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and vice versa.

Fig. 5 Master Slave Flip flop

Working of a master slave flip flop –

When the clock pulse goes high, the slave is isolated; J and K inputs can affect the state of the system. The slave flip-flop is isolated when the CP goes low. When the CP goes back to 0, information is transmitted from the master flip-flop to the slave flip-flop and output is obtained.

The master flip flop is positive level triggered and the slave flip flop is negative level triggered, hence the master responds prior to the slave.

If J=0 and K=1, Q’ = 1 then the master goes to the K input of the slave and the clock forces the slave to reset therefore the slave copies the master.

If J=1 and K=0, Q = 1 then the master goes to the J input of the slave and the Negative transition of the clock sets the slave and thus copy the master.

If J=1 and K=1, the master toggles on the positive transition and the slave toggles on the negative transition of the clock.

If J=0 and K=0, the flip flop becomes disabled and Q remains unchanged.

Timing Diagram of a Master flip flop –

When the CP = 1 then the output of master is high and remains high till CP = 0 because the state is stored.

Now the output of master becomes low when the clock CP = 1 and remains low until the clock becomes high again.

Thus, toggling takes place for a clock cycle.

When the CP = 1 then the master is operational but not the slave.

When the clock is low, the slave becomes operational and remains high until the clock again becomes low.

Toggling takes place during the whole process since the output changes once in a cycle.

This makes the Master-Slave J-K flip flop a Synchronous device which passes data with the clock signal.

Key takeaway

If J=0 and K=1, Q’ = 1 then the master goes to the K input of the slave and the clock forces the slave to reset therefore the slave copies the master.

If J=1 and K=0, Q = 1 then the master goes to the J input of the slave and the Negative transition of the clock sets the slave and thus copy the master.

If J=1 and K=1, the master toggles on the positive transition and the slave toggles on the negative transition of the clock.

If J=0 and K=0, the flip flop becomes disabled and Q remains unchanged.

3.4 Characteristics equation and state diagram of each FFs

State Table

The state table representation of a sequential circuit consists of three sections labeled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state.

State Diagram

In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically by a state diagram. In this diagram, a state is represented by a circle, and the transition between states is indicated by directed lines (or arcs) connecting the circles.

3.5 Conversion of Flip-Flops

EXCITATION TABLE:

i) SR To JK Flipflop

Excitation Functions:

ii) Convert SR to D Flip-Flop:

Excitation Functions:

S = D

R = D ‘

Key takeaway

3.6 Analysis of Clocked Sequential circuits

Some flip-flops have asynchronous inputs that are used to force the flip-flop to a particular state independently of the clock

The input that sets the flip-flop to 1 is called preset or direct set. The input that clears the flip-flop to 0 is called clear or direct reset.

When power is turned on in a digital system, the state of the flip-flops is unknown. The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation.

The knowledge of the type of flip-flops and a list of the Boolean expressions of the combinational circuit provide the information needed to draw the logic diagram of the sequential circuit. The part of the combinational circuit that gene rates external outputs is described algebraically by a set of Boolean functions called output equations. The part of the circuit that generates the inputs to flip-flops is described algebraically by a set of Boolean functions called flip-flop input equations (or excitation equations).

The information available in a state table can be represented graphically in the form of a state diagram. In this type of diagram, a state is represented by a circle and the (clock-triggered) transitions between states are indicated by directed lines connecting the circles.

The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table (transition table). The table has four parts present state, next state, inputs and outputs.

In general, a sequential circuit with 'm' flip-flops and 'n' inputs needs 2m+n rows in the state table.

Positive Edge Triggered D Flip-flop

A circuit diagram of a Positive edge triggered D Flip-flop is shown as below. It has an additional reset input connected to the three NAND gates.

Fig: Circuit Diagram

Fig 7 Symbol

Fig 8 State Table

When the reset input is 0 it forces output Q' to Stay at 1 which clears output Q to 0 thus resetting the flip-flop.

Two other connections from the reset input ensure that the S input of the third SR latch stays at logic 1 while the reset input is at 0 regardless of the values of D and Clk.

Function table suggests that:

When R = 0, the output is set to 0 (independent of D and Clock).
The clock at Clock is shown with an upward arrow to indicate that the flip-flop triggers on the positive edge of the clock.
The value in D is transferred to Q with every positive-edge clock signal provided that R = 1.

Analysis with D Flip-Flops

The input equation of a D Flip-flop is given by DA = A ⊕ x ⊕ y. DA means a D Flip-flop with output A.

The x and y variables are the inputs to the circuit. No output equations are given, which implies that the output comes from the output of the flip-flop.

The state table has one column for the present state of flip-flop 'A' two columns for the two inputs, and one column for the next state of A.

The next-state values are obtained from the state equation A (t + 1) = A ⊕ x ⊕ y.

The expression specifies an odd function and is equal to 1 when only one variable is 1 or when all three variables are 1.

Fig 9 Circuit Diagram

Fig 10 State Table

Analysis with JK Flip-Flops

The circuit can be specified by the flip-flop input equations:

JA = B; KA = Bx'
JB = x'; KB = A'x + Ax' = A ⊕ x

The next state of each flip-flop is evaluated from the corresponding J and K inputs and the characteristic table of the JK flip-flop listed as:

When J = 1 and K = 0 the next state is 1
When J = 0 and K = 1 the next state is 0
When J = 0 and K = 0 there is no change of state and the next-state value is the same as that of the present state.
When J = K = 1, the next-state bit is the complement of the present-state bit.

Fig 11 Circuit Diagram

Fig 12 State Table

The characteristic equations for the flip-flops are

A (t + 1) = JA' + K'A
B (t + 1) = JB' + K'B

This gives us the state equation of A by substituting the values of JA, KA

A (t + 1) = BA' + (Bx')'A = A'B + AB' + Ax

The state equation provides the bit values for the column headed "Next State" for A in the state table. Similarly, the state equation for flip-flop B can be derived from the characteristic equation by substituting the values of JB and KB.:

B (t + 1) = x'B' + (A ⊕ x)'B = B'x' + ABx + A'Bx'

Analysis with T Flip-Flops

The circuit can be specified by the characteristic equations:

Q(t+1) = T ⊕ Q = T'Q + TQ'

The sequential circuit has two flip-flops A and B, one input x, and one output y and can be described algebraically by two input equations and an output equation.

TA = Bx
TB = x
y = AB

The state table for the circuit is listed below. The values for y are obtained from the output equation. The values for the next state can be derived from the state equations by substituting TA and TB in the characteristic equations yielding:

A (t + 1) = (Bx)' A + (Bx)A' = AB' + Ax' + A'Bx
B (t + 1) = x ⊕ B

Fig 13 Circuit Diagram

Fig 14 State Table

3.7 Mealy and Moore Models of Finite State Machines.

Mealy Machine

A Mealy Machine is an FSM whose output depends on the present state as well as the present input.

It can be described by a 6 tuple (Q, ∑, O, δ, X, q0) where −

Q is a finite set of states.

∑ is a finite set of symbols calling the input alphabet.

is a finite set of symbols called the output alphabet.

δ is the input transition function where δ: Q × ∑ → Q

X is the output transition function where X: Q × ∑ → O

q0 is the initial state from where any input is processed (q0 ∈ Q).

The state table of a Mealy Machine is shown below −

Present state	Next state
	input = 0		input = 1
	State	Output	State	Output
→ a	b	x1	c	x1
b	b	x2	d	x3
c	d	x3	c	x1
d	d	x3	d	x2

The state diagram of the above Mealy Machine is −

State Diagram of Mealy Machine

Moore Machine

Moore machine is an FSM whose outputs depend on only the present state.

A Moore machine can be described by a 6 tuple (Q, ∑, O, δ, X, q0) where −

Q is a finite set of states.

∑ is a finite set of symbols calling the input alphabet.

is a finite set of symbols called the output alphabet.

δ is the input transition function where δ: Q × ∑ → Q

X is the output transition function where X: Q → O

q0 is the initial state from where any input is processed (q0 ∈ Q).

The state table of a Moore Machine is shown below −

Present state	Next State		Output
Present state	Input = 0	Input = 1	Output
→ a	b	c	x2
b	b	d	x1
c	c	d	x2
d	d	d	x3

The state diagram of the above Moore Machine is −

Moore Machine State Diagram

Mealy Machine vs. Moore Machine

The following table highlights the points that differentiate a Mealy Machine from a Moore Machine.

Mealy Machine	Moore Machine
Output depends both upon the present state and the present input	Output depends only upon the present state.
Generally, it has fewer states than Moore Machine.	Generally, it has more states than Mealy Machine.
The value of the output function is a function of the transitions and the changes, when the input logic on the present state is done.	The value of the output function is a function of the current state and the changes at the clock edges, whenever state changes occur.
Mealy machines react faster to inputs. They generally react in the same clock cycle.	In Moore machines, more logic is required to decode the outputs resulting in more circuit delays. They generally react one clock cycle later.

References:

Digital Design, 3rd Edition, Moris M. Mano, Pearson Education.

Fundamentals of digital circuits, 8th edition, A. Anand Kumar, PHI

Digital Fundamentals, 5th Edition, T.L. Floyd and R.P. Jain, Pearson Education, New Delhi.

Digital Electronics, G. K. Kharate, Oxford University Press.

Digital Systems – Principles and Applications, 10th Edition, Ronald J. Tocci, Neal S. Widemer and Gregory L. Moss, Pearson Education.

A First Course in Digital System Design: An Integrated Approach, India Edition, John P. Uyemura, PWS Publishing Company, a division of Thomson Learning Inc.

Digital Systems – Principles and Applications, 10th Edition, Ronald J. Tocci, Neal S. Widemer and Gregory L. Moss, Pearson Education.

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