2.1 Bipolar Junction Transistor Transistor Construction Operation Amplification action | unit 2 bipolar junction transistor

EDEE

Unit-2

Bipolar Junction Transistor

2.1 Bipolar Junction Transistor: Transistor Construction, Operation, Amplification action

It is an electronic device with three terminals namely base, emitter and collector.

It is made of three layers consisting of two n and one p named as npn transistor or one n and two p named as pnp transistor.

Fig 1 : (a) pnp transistor (b) npn transistor

Basic theory and operation of PNP and NPN transistors:

The operation is explained by considering the PNP transistor. The operation of NPN transistor varies with a little exchange of roles played by the electrons and holes.

Now, there is a reduction in the width of the depletion layer due to the applied bias which results in a heavy flow of majority carriers from p to n type material.

On removing the base emitter bias of pnp transistor we get forward biasing of transistor.

Fig. 2: Forward bias of pnp transistor (Ref. 2)

Now if the flow of majority carrier is zero then the flow of minority carrier leads to reverse bias condition.

When both the biasing potentials are applied simultaneously then both the majority and minority carriers start flowing.

Here the n type material is very small and has less conductivity hence the magnitude of base current is of the order of microamperes

Fig. 3: pnp transistor (Ref. 2)

Now applying Kirchoff’s law we get

Ie = Ic + Ib

Hence, the emitter current is sum of the collector current and base current.

The collector current has two components : the majority (Icm) and minority currents (Ico).

Ic = Icm + Ico

Ico is known as the leakage current and is measured in micro or nano amperes.

It is temperature sensitive and can affect the stability of the system with high temperature requirement if not considered properly.

2.2 Common Base, Common Emitter, Common Collector Configuration

The notation and symbols of pnp and npn transistors are given below:

Fig. 4: PNP CB and NPN CB (Ref. 2)

Here the base is common to both the input and output sides of the configuration.

The flow of holes will govern the direction of current.

Hence, Ic = Ib + Ie

Where Ic, Ib, Ie are the collector, base and emitter currents respectively.

The graphical symbol of the PNP common base configuration is

Fig. 5 : PNP common base(Ref. 2)

The arrow in the above symbol shows the direction of emitter current in the device.

Now, to study the behavior of the device we require two characteristics:

Input Characteristic Curve

Fig.6: Input Characteristic Curve (Ref. 2)

It is the relation between the input current IE to the input voltage VBE for various levels of output voltage VCB.

It is also known as driving point characteristics.

Output Characteristic Curve

Fig.7 : Output Characteristic Curve (Ref. 2)

It is the relation between the output current IC to the output voltage VCB for various levels of input current IE.

It is also known as collector set of characteristics.

It has three basic regions:

Active Region

Here, base-emitter junction is forward biased and collector-base junction is reverse biased.

As input current IE increases above zero, output current IC increases to a magnitude equal to IE as determined by the basic transistor current relationship.

So the first approximation determined by the curve is

IC ≈ IE

2. Cut-off Region

It is defined as the region where the collector current IC is equal to 0A.

Here, the base-emitter junction and the collector-base junction both are in reverse bias.

3. Saturation Region

It is the region that lies towards the left of VCB = 0V.

Here, the base-emitter junction and the collector-base junction both are in forward bias.

Common Emitter Configuration

The notation and symbols of npn and pnp transistors are given below:

Fig. 8: NPN CE and PNP CE (Ref. 2)

In the above figure all the currents are shown in their actual conventional directions.

The current relation developed earlier is still applicable,

IE = IB + IC

Where IE , IB , IC are the collector, base and emitter currents respectively.

The graphical symbol of the PNP common emitter configuration is

Fig. 9 : PNP common emitter (Ref. 2)

Now, to study the behavior of the device we require two characteristics:

Input Characteristic Curve

Fig.10: Input Characteristic Curve (Ref. 2)

It is the graph between the input current IB to the input voltage VBE for a range of values of output voltage VCE.

Note that the magnitude IB of is in micro amperes and that of IC is in milli amperes.

Output Characteristic Curve

Fig.11: Output Characteristic Curve (Ref. 2)

It is the graph between the output current IC to the output voltage VCE for a range of values of input current IB.

It has three basic regions:

 Active Region

Here, the base-emitter junction is forward biased and collector base junction is reverse biased.

These are the same conditions that existed in the active region of the common base configuration.

This can be employed for voltage, current or power amplification.

 Cut-off Region

Here IC is not equal to zero when IB is zero.

For linear amplification purposes, it is defined as IC = ICEO .

The region below IB = 0µA is to be avoided for undistorted output signal.

When the transistor is used as a switch, the condition should be ideally IC = 0mA for a chosen VCE voltage.

 Saturation Region

It is the region that lies towards the left of VCE = 0V.

Common Collector Configuration

The notation and symbols of npn and pnp transistors are given below:

Fig. 12: NPN CC and PNP CC (Ref. 2)

In the above figure all the currents are shown in their actual conventional directions.

It is used for impedence matching purposes as it has high input impedence and low output impedence.

It can be designed using common emitter characteristics.

The output characteristics of common collector is same as that of common emitter configuration for all practical purposes.

The output characteristics are a plot between IE versus VCE for all values of IB.

The input current of common collector is same as that of common emitter configuration.

Here the region of operation will ensure that maximum ratings are not being exceeded and output ratings have minimum distortion.

Fig.13: Output Characteristic Curve (Ref. 2)

The characteristics specifying the minimum VCE that can be applied without entering the non-linear region is saturation region.

The maximum power dissipation is given by,

P = VCE . IC

2.3 Field Effect Transistor: Construction and Characteristic of JFETs, Transfer Characteristic

An FET is a three-terminal amplifying device.

Its terminals are source, gate, and drain, which acts respectively like emitter, base, and collector of a normal transistor.

There are two distinct families of FETs.

The first is known as ‘junction-gate’ types of FETs or JUGFET or JFET.

The second family is called ‘insulated-gate’ FETs or Metal Oxide Semiconductor FETs or MOSFET.

‘N-channel’ and ‘p-channel’ are the two versions of both types of FET.

Fig.14: FET

Operation

N-channel FET consists of n-type semiconductor material with a drain terminal and a source terminal at opposite ends.

A p-type gate is joined in the middle section of the n-type bar, thus forming a p-n junction.

The drain terminal is connected to a positive supply and the gate is biased at a value that is negative (or equal) to the source voltage, thus reverse-biasing the JFET’s internal p-n junction, and accounting for its very high input impedance.

When gate = 0V, a current flow from drain to source via a conductive ‘channel’ and the n-type bar is formed.

When gate = negative , a high resistance region is formed within the junction, thus reduces the magnitude of the drain-to-source current and width of the n-type conduction channel.

Thus, the basic JFET passes maximum current when its gate bias is zero, and its current is reduced or ‘depleted’ when the gate bias is increased. It is thus known as a ‘depletion-type’ n-channel JFET.

I-V characteristics

Output Characteristics or Drain Characteristics

In the absence of external bias: In this case, as there is no voltage between gate and source terminal, thus, the drain current will flow from drain terminal to source terminal. We have already discussed in the working of JFET that majority charge carriers flow from source to drain and as a consequence of which the current flows from drain to source.

2. With external bias: When the external bias is applied to the gate-source terminal, the gate-source terminal becomes reversed bias externally. Obviously, if we are supplying an external voltage, then we can achieve the pinch-off point quite early as compared to the circuit which is not biased.

Transfer Characteristics

The transfer characteristics can be determined by observing different values of drain current with variation in gate-source voltage provided that the drain-source voltage should be constant. The transfer characteristics are just opposite to drain characteristics.

2.4 MOSFET (MOS) (Depletion and Enhancement) Type, Transfer

Characteristic

 The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a semiconductor device which is widely used for switching and amplifying electronic signals in the electronic devices.

 It is a core of integrated circuit and is designed and fabricated in a single chip because of its small size.

 It is a four-terminal device with source(S), gate (G), drain (D) and body (B) terminals.

 The body of the MOSFET is connected to the source hence making it a three-terminal device like field effect transistor. It can be used in both analog and digital circuits.

Operation

The MOSFET works by electronically varying the width of a channel along which charge carriers flow (electrons or holes).

The charge carriers enter the channel through source and exit via the drain.

The width of the channel is controlled by the gate voltage which is located between source and drain.

It is insulated from the channel near an extremely thin layer of metal oxide.

Function:

Depletion Mode

When there is no voltage on the gate, the channel shows maximum conductance. When the voltage on the gate is either positive or negative, the channel conductivity decreases.

2. Enhancement Mode

The device does not conduct when there is no voltage on the gate. As the voltage increases on the gate, the better the device can conduct.

Working:

The aim of the MOSFET is to be able to control the voltage and current flow between the source and drain. It works like a switch.

The working depends upon the MOS capacitor.

The MOS capacitor is the main part of MOSFET.

The semiconductor surface at the below oxide layer is located between source and drain terminal. It can be inverted from p-type to n-type by applying positive or negative gate voltages respectively.

When the positive gate voltage is applied, the holes present under the oxide layer repel with a repulsive force and holes are pushed downward with the substrate.

The depletion region populated by the negative charges is the acceptor atoms. The positive voltage also attracts electrons. Now, if a voltage is applied between the drain and source, the current flows between the source and drain and the gate voltage controls the electrons in the channel.

References:

1 “Electronic devices and circuit theory” by Boylestead and Nashelsky, Pearson

2 “Electronic principle” by Albert Malvino and Davis J Bates, TMH

3 “Integrated Electronics”, By Jacob Millman and Christos Halkias

Sign Up

Index

Notes

Highlighted

Underlined

Browse by Topics

Notes

Highlighted

Underlined