Unit - 4

Input- output, exceptions and interrupts

4.1 I/O Addressing

The 80386 allows input/output to be performed in either of two ways:

1. By means of a separate I/O address space (using specific I/O instructions)

2. By means of memory-mapped I/O (using general-purpose operand manipulation instructions).

4.1.1 I/O Address Space

1. The 80386 provides a separate I/O address space, distinct from physical memory, that can be used to address the input/output ports that are used for external 16 devices.

2. The I/O address space consists of 2^(16) (64K) individually addressable 8-bit ports; any two consecutive 8-bit ports can be treated as a 16-bit port; and four consecutive 8-bit ports can be treated as a 32-bit port. Thus, the I/O address space can accommodate up to 64K 8-bit ports, up to 32K 16-bit ports, or up to 16K 32-bit ports.

3. The program can specify the address of the port in two ways. Using an immediate byte constant, the program can specify:

i)            256 8-bit ports numbered 0 through 255.

ii)            128 16-bit ports numbered 0, 2, 4, . . . , 252, 254.

iii)            64 32-bit ports numbered 0, 4, 8, . . . , 248, 252.

4. Using a value in DX, the program can specify:

i)            8-bit ports numbered 0 through 65535

ii)            16-bit ports numbered 0, 2, 4, . . . , 65532, 65534

iii)            32-bit ports numbered 0, 4, 8, . . . , 65528, 65532

5. The 80386 can transfer 32, 16, or 8 bits at a time to a device located in the I/O space. Like double words in memory, 32-bit ports should be aligned at addresses evenly divisible by four so that the 32 bits can be transferred in a single bus access.

6. Like words in memory, 16-bit ports should be aligned at even-numbered addresses so that the 16 bits can be transferred in a single bus access. An 8-bit port may be located at either an even or odd address.

7. The instructions IN and OUT move data between a register and a port in the I/O address space. The instructions INS and OUTS move strings of data between the memory address space and ports in the I/O address space.

4.1.2 Memory-Mapped I/O

1. I/O devices also may be placed in the 80386 memory address space. As long as the devices respond like memory components, they are indistinguishable to the processor.

2. Memory-mapped I/O provides additional programming flexibility. Any instruction that references memory may be used to access an I/O port located in the memory space

2.  For example, the MOV instruction can transfer data between any register and a port; and the AND, OR, and TEST instructions may be used to manipulate bits  Memory-mapped I/O performed via the full instruction set maintains the full complement of addressing modes for selecting the desired I/O device (e.g., direct address, indirect address, base register, index register, scaling).

Key takeaways

1. The I/O address space consists of 2^(16) (64K) individually addressable 8-bit ports; any two consecutive 8-bit ports can be treated as a 16-bit port; and four consecutive 8-bit ports can be treated as a 32-bit port.
2. Memory-mapped I/O provides additional programming flexibility. Any instruction that references memory may be used to access an I/O port located in the memory space.

4.2 I/O Instructions

1. The I/O instructions of the 80386 provide access to the processor's I/O ports for the transfer of data to and from peripheral devices. These instructions have as one operand the address of a port in the I/O address space. There are two classes of I/O instruction:

i)              Those that transfer a single item (byte, word, or doubleword) located in a register.

ii)              Those that transfer strings of items (strings of bytes, words, or doublewords) located in memory. These are known as "string I/O instructions" or "block I/O instructions".

4.2.1 Register I/O Instructions

1. The I/O instructions IN and OUT are provided to move data between I/O ports and the EAX (32-bit I/O), the AX (16-bit I/O), or AL (8-bit I/O) general registers. IN and OUT instructions address I/O ports either directly, with the address of one of up to 256 port addresses coded in the instruction, or indirectly via the DX register to one of up to 64K port addresses.

2. IN (Input from Port) transfers a byte, word, or double word from an input port to AL, AX, or EAX. If a program specifies AL with the IN instruction, the processor transfers 8 bits from the selected port to AL. If a program specifies AX with the IN instruction, the processor transfers 16 bits from the port to AX. If a program specifies EAX with the IN instruction, the processor transfers 32 bits from the port to EAX.

3.OUT(Output to Port) transfers a byte, word, or double word to an output port from AL, AX, or EAX. The program can specify the number of the port using the same methods as the IN instruction.

4.2.2 Block I/O Instructions

1. The block (or string) I/O instructions INS and OUTS move blocks of data between I/O ports and memory space. Block I/O instructions use the DX register to specify the address of a port in the I/O address space. INS and OUTSuse DX to specify:

• 8-bit ports numbered 0 through 65535
• 16-bit ports numbered 0, 2, 4, . . . , 65532, 65534
• 32-bit ports numbered 0, 4, 8, . . . , 65528, 65532

2. Block I/O instructions use either SI or DI to designate the source or destination memory address. For each transfer, SI or DI are automatically either incremented or decremented as specified by the direction bit in the flags register.

3. INS and OUTS, when used with repeat prefixes, cause block input or output operations. REP, the repeat prefix, modifies INS and OUTS to provide a means of transferring blocks of data between an I/O port and memory. These block I/O instructions are string primitives .

4.  They simplify programming and increase the speed of data transfer by eliminating the need to use a separate LOOP instruction or an intermediate register to hold the data.

5. The string I/O primitives can operate on byte strings, word strings, or doubleword strings. After each transfer, the memory address in ESI or EDI is updated by 1 for byte operands, by 2 for word operands, or by 4 for doubleword operands.

6. The value in the direction flag (DF) determines whether the processor automatically increments ESI or EDI (DF=0) or whether it automatically decrements these registers (DF=1).

Key takeaways

1. The I/O instructions of the 80386 provide access to the processor's I/O ports for the transfer of data to and from peripheral devices.
2. IN (Input from Port) transfers a byte, word, or double word from an input port to AL, AX, or EAX. If a program specifies AL with the IN instruction, the processor transfers 8 bits from the selected port to AL.
3. INS and OUTS, when used with repeat prefixes, cause block input or output operations.

4.3 Protection and I/O

1. Two mechanisms provide protection for I/O functions:

• The IOPL field in the EFLAGS register defines the right to use I/O-related instructions.
• The I/O permission bit map of a 80386 TSS segment defines the right to use ports in the I/O address space.

2. These mechanisms operate only in protected mode, including virtual 8086 mode; they do not operate in real mode. In real mode, there is no protection of the I/O space; any procedure can execute I/O instructions, and any I/O port can be addressed by the I/O instructions.

4.3.1 I/O Privilege Level

1. Instructions that deal with I/O need to be restricted but also need to be executed by procedures executing at privilege levels other than zero. For this reason, the processor uses two bits of the flags register to store the I/O privilege level (IOPL). The IOPL defines the privilege level needed to execute I/O-related instructions.

The following instructions can be executed only if CPL <= IOPL:

(i)        IN -- Input

(ii)              INS -- Input String

(iii)           OUT -- Output

(iv)            OUTS -- Output String

(v)              CLI -- Clear Interrupt-Enable Flag

(vi)            STI -- Set Interrupt-Enable

2. These instructions are called "sensitive" instructions, because they are sensitive to IOPL.

3. To use sensitive instructions, a procedure must execute at a privilege level at least as privileged as that specified by the IOPL (CPL <= IOPL). Any attempt by a less privileged procedure to use a sensitive instruction results in a general protection exception.

4. Because each task has its own unique copy of the flags register, each task can have a different IOPL.

5. A task whose primary function is to perform I/O (a device driver) can benefit from having an IOPL of three, thereby permitting all procedures of the task to perform I/O. Other tasks typically have IOPL set to zero or one, reserving the right to perform I/O instructions for the most privileged procedures.

4.3.2 I/O Permission Bit Map

1. The I/O instructions that directly refer to addresses in the processor's I/O space are IN, INS, OUT, OUTS. The 80386 has the ability to selectively trap references to specific I/O addresses.

2. The structure that enables selective trapping is the I/O Permission Bit Map in the TSS segment . The I/O permission map is a bit vector. The size of the map and its location in the TSS segment are variable.

3. The processor locates the I/O permission map by means of the I/O map base field in the fixed portion of the TSS. The I/O map base field is 16 bits wide and contains the offset of the beginning of the I/O permission map. The upper limit of the I/O permission map is the same as the limit of the TSS segment.

4. In protected mode, when it encounters an I/O instruction (IN, INS, OUT, or OUTS), the processor first checks whether CPL <= IOPL. If this condition is true, the I/O operation may proceed.

5.  If not true, the processor checks the I/O permission map. (In virtual 8086 mode, the processor consults the map without regard for IOPL .

6. Each bit in the map corresponds to an I/O port byte address; for example, the bit for port 41 is found at I/O map base + 5, bit offset 1.

7. The processor tests all the bits that correspond to the I/O addresses spanned by an I/O operation; for example, a doubleword operation tests four bits corresponding to four adjacent byte addresses. If any tested bit is set, the processor signals a general protection exception. If all the tested bits are zero, the I/O operation may proceed.

Key takeaways

1. These mechanisms operate only in protected mode, including virtual 8086 mode; they do not operate in real mode
2. To use sensitive instructions, a procedure must execute at a privilege level at least as privileged as that specified by the IOPL (CPL <= IOPL). Any attempt by a less privileged procedure to use a sensitive instruction results in a general protection exception.
3. The processor locates the I/O permission map by means of the I/O map base field in the fixed portion of the TSS. The I/O map base field is 16 bits wide and contains the offset of the beginning of the I/O permission map.
4. Each bit in the map corresponds to an I/O port byte address; for example, the bit for port 41 is found at I/O map base + 5, bit offset 1.

Part 2 exceptions and interrupts

4.4 Identifying Interrupts

1. The processor associates an identifying number with each different type of interrupt or exception.

2. The NMI and the exceptions recognized by the processor are assigned predetermined identifiers in the range 0 through 31. Not all of these numbers are currently used by the 80386; unassigned identifiers in this range are reserved by Intel for possible future expansion.

3. The identifiers of the maskable interrupts are determined by external interrupt controllers (such as Intel's 8259A Programmable Interrupt Controller) and communicated to the processor during the processor's interrupt-acknowledge sequence.

4. The numbers assigned by an 8259A PIC can be specified by software. Any numbers in the range 32 through 255 can be used. Table shows the assignment of interrupt and exception identifiers.

5. Exceptions are classified as faults, traps, or aborts depending on the way they are reported and whether restart of the instruction that caused the exception is supported.

5.1 Faults

Faults are exceptions that are reported "before" the instruction causingthe exception. Faults are either detected before the instruction begins to execute, or during execution of the instruction. If detected during the instruction, the fault is reported with the machine restored to a state that permits the instruction to be restarted.

5.2 Traps

A trap is an exception that is reported at the instruction boundary immediately after the instruction in which the exception was detected.

5.3 Aborts

An abort is an exception that permits neither precise location of the instruction causing the exception nor restart of the program that caused the exception. Aborts are used to report severe errors, such as hardware errors and inconsistent or illegal values in system tables.

Interrupt and Exception ID Assignments

Key takeaways

1. The NMI and the exceptions recognized by the processor are assigned predetermined identifiers in the range 0 through 31.
2. The numbers assigned by an 8259A PIC can be specified by software. Any numbers in the range 32 through 255 can be used.
3. Faults are either detected before the instruction begins to execute, or during execution of the instruction.

4.5 Enabling and Disabling Interrupts

1. The processor services interrupts and exceptions only between the end of one instruction and the beginning of the next.

2.  When the repeat prefix is used to repeat a string instruction, interrupts and exceptions may occur between repetitions. Thus, operations on long strings do not delay interrupt response.

3. Certain conditions and flag settings cause the processor to inhibit certain interrupts and exceptions at instruction boundaries.

4.5.1 NMI Masks Further NMIs

While an NMI handler is executing, the processor ignores further interrupt signals at the NMI pin until the next IRET instruction is executed.

4.5.2 IF Masks INTR

1. The IF (interrupt-enable flag) controls the acceptance of external interrupts signalled via the INTR pin. When IF=0, INTR interrupts are inhibited; when IF=1, INTR interrupts are enabled.

2. As with the other flag bits, the processor clears IF in response to a RESET signal. The instructions CLI and STI alter the setting of IF.

3. CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) explicitly alter IF (bit 9 in the flag register). These instructions may be executed only if CPL <= IOPL. A protection exception occurs if they are executed when CPL > IOPL.

4. The IF is also affected implicitly by the following operations:

• The instruction PUSHF stores all flags, including IF, in the stack where they can be examined.
• Task switches and the instructions POPF and IRET load the flags register; therefore, they can be used to modify IF.
• Interrupts through interrupt gates automatically reset IF, disabling interrupts.

4.5.3 RF Masks Debug Faults

The RF bit in EFLAGS controls the recognition of debug faults. This permits debug faults to be raised for a given instruction at most once, no matter how many times the instruction is restarted.

4.5.4 MOV or POP to SS Masks Some Interrupts and Exceptions

1. Software that needs to change stack segments often uses a pair of instructions; for example:

MOV SS, AX

MOV ESP, StackTop

2. If an interrupt or exception is processed after SS has been changed but before ESP has received the corresponding change, the two parts of the stack pointer SS:ESP are inconsistent for the duration of the interrupt handler or exception handler.

3. To prevent this situation, the 80386, after both a MOV to SS and a POP to SS instruction, inhibits NMI, INTR, debug exceptions, and single-step traps at the instruction boundary following the instruction that changes SS.

4. Some exceptions may still occur; namely, page fault and general protection fault. Always use the 80386 LSS instruction, and the problem will not occur.

Key takeaways

1. When the repeat prefix is used to repeat a string instruction, interrupts and exceptions may occur between repetitions
2. CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) explicitly alter IF (bit 9 in the flag register).
3. The RF bit in EFLAGS controls the recognition of debug faults
4. If an interrupt or exception is processed after SS has been changed but before ESP has received the corresponding change, the two parts of the stack pointer SS: ESP are inconsistent for the duration of the interrupt handler or exception handler.

4.6 Priority among Simultaneous Interrupts and Exceptions

1. If more than one interrupt or exception is pending at an instruction boundary, the processor services one of them at a time.

2.  The processor first services a pending interrupt or exception from the class that has the highest priority, transferring control to the first instruction of the interrupt handler.

3. Lower priority exceptions are discarded; lower priority interrupts are held pending. Discarded exceptions will be rediscovered when the interrupt handler returns control to the point of interruption.

Key takeaways

1. The processor first services a pending interrupt or exception from the class that has the highest priority, transferring control to the first instruction of the interrupt handler.

4.7 Interrupt Descriptor Table

1. The interrupt descriptor table (IDT) associates each interrupt or exception identifier with a descriptor for the instructions that service the associated event. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors.

2. Unlike the GDT and LDTs, the first entry of the IDT may contain a descriptor. To form an index into the IDT, the processor multiplies the interrupt or exception identifier by eight.

3. Because there are only 256 identifiers, the IDT need not contain more than 256 descriptors. It can contain fewer than 256 entries; entries are required only for interrupt identifiers that are actually used.

4. The IDT may reside anywhere in physical memory. As  the processor locates the IDT by means of the IDT register (IDTR). The instructions LIDT and SIDT operate on the IDTR. Both instructions have one explicit operand: the address in memory of a 6-byte area.

5. LIDT (Load IDT register) loads the IDT register with the linear base address and limit values contained in the memory operand.

6.  This instruction can be executed only when the CPL is zero. It is normally used by the initialization logic of an operating system when creating an IDT. An operating system may also use it to change from one IDT to another.

7. SIDT (Store IDT register) copies the base and limit value stored in IDTR to a memory location. This instruction can be executed at any privilege level.

8. Table  Priority Among Simultaneous Interrupts and Exceptions

Priority   Class of Interrupt or Exception

HIGHEST    Faults except debug faults

Trap instructions INTO, INT n, INT 3

Debug traps for this instruction

Debug faults for next instruction

NMI interrupt

LOWEST     INTR interrupt

Key takeaways

1. Unlike the GDT and LDTs, the first entry of the IDT may contain a descriptor. To form an index into the IDT, the processor multiplies the interrupt or exception identifier by eight.
2. The interrupt descriptor table (IDT) associates each interrupt or exception identifier with a descriptor for the instructions that service the associated event.
3. An operating system may also use it to change from one IDT to another.

4.8 IDT Descriptors

1. The IDT may contain any of three kinds of descriptor:

Task gates

1. A task gate descriptor provides an indirect, protected reference to a TSS.

The SELECTOR field of a task gate must refer to a TSS descriptor. The value of the RPL in this selector is not used by the processor.

2. The DPL field of a task gate controls the right to use the descriptor to cause a task switch. A procedure may not select a task gate descriptor unless the maximum of the selector's RPL and the CPL of the procedure is numerically less than or equal to the DPL of the descriptor. This constraint prevents untrusted procedures from causing a task switch.

Interrupt gates

1. An interrupt gate or trap gate points indirectly to a procedure which will execute in the context of the currently executing task .

2. The selector of the gate points to an executable-segment descriptor in either the GDT or the current LDT. The offset field of the gate points to the beginning of the interrupt or exception handling procedure.

Trap gates

1.An trap gate points indirectly to a procedure which will execute in the context of the currently executing task The selector of the gate points to an executable-segment descriptor in either the GDT or the current LDT.

2. The offset field of the gate points to the beginning of the interrupt or exception handling procedure.

Key takeaways

1. A task gate descriptor provides an indirect, protected reference to a TSS.

1. 2.An interrupt gate points indirectly to a procedure which will execute in the context of the currently executing task
2. The offset field of the gate points to the beginning of the interrupt or exception handling procedure.

4.9 Interrupt Tasks and Interrupt Procedures

1. Just as a CALL instruction can call either a procedure or a task, so an interrupt or exception can "call" an interrupt handler that is either a procedure or a task. When responding to an interrupt or exception, the processor uses the interrupt or exception identifier to index a descriptor in the IDT.

2. If the processor indexes to an interrupt gate or trap gate, it invokes the handler in a manner similar to a CALL to a call gate. If the processor finds a task gate, it causes a task switch in a manner similar to a CALL to a task gate.

4.9.1 Interrupt Procedures

1. An interrupt gate or trap gate points indirectly to a procedure which will execute in the context of the currently executing task The selector of the gate points to an executable-segment descriptor in either the GDT or the current LDT. The offset field of the gate points to the beginning of the interrupt or exception handling procedure.

4.9.1.1 Stack of Interrupt Procedure

1. Just as with a control transfer due to a CALL instruction, a control transfer to an interrupt or exception handling procedure uses the stack to store the information needed for returning to the original procedure.

2.  An interrupt pushes the EFLAGS register onto the stack before the pointer to the interrupted instruction.

3. Certain types of exceptions also cause an error code to be pushed on the stack. An exception handler can use the error code to help diagnose the exception.

4.9.1.2 Returning from an Interrupt Procedure

1. An interrupt procedure also differs from a normal procedure in the method of leaving the procedure.

2. The IRET instruction is used to exit from an interrupt procedure. IRET is similar to RET except that IRET increments ESP by an extra four bytes (because of the flags on the stack) and moves the saved flags into the EFLAGS register.

3.  The IOPL field of EFLAGS is changed only if the CPL is zero. The IF flag is changed only if CPL <= IOPL.

4.9.1.3 Flags Usage by Interrupt Procedure

1. Interrupts that vector through either interrupt gates or trap gates cause TF (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. By this action the processor prevents debugging activity that uses single-stepping from affecting interrupt response. A subsequent IRET instruction restores TF to the value in the EFLAGS image on the stack.

2. The difference between an interrupt gate and a trap gate is in the effect on IF (the interrupt-enable flag).

3. An interrupt that vectors through an interrupt gate resets IF, thereby preventing other interrupts from interfering with the current interrupt handler. A subsequent IRET instruction restores IF to the value in the EFLAGS image on the stack. An interrupt through a trap gate does not change IF.

4.9.1.4 Protection in Interrupt Procedures

1. The privilege rule that governs interrupt procedures is similar to that for procedure calls: the CPU does not permit an interrupt to transfer control to a procedure in a segment of lesser privilege (numerically greater privilege level) than the current privilege level.

2.  An attempt to violate this rule results in a general protection exception. Because occurrence of interrupts is not generally predictable, this privilege rule effectively imposes restrictions on the privilege levels at which interrupt and exception handling procedures can execute.

3. Either of the following strategies can be employed to ensure that the privilege rule is never violated.

4. Place the handler in a conforming segment. This strategy suits the handlers for certain exceptions (divide error, for example)

5. Such a handler must use only the data available to it from the stack. If it needed data from a data segment, the data segment would have to have privilege level three, thereby making it unprotected.

Place the handler procedure in a privilege level zero segment.

4.9.2 Interrupt Tasks

1. A task gate in the IDT points indirectly to a task, The selector of the gate points to a TSS descriptor in the GDT.

2. When an interrupt or exception vectors to a task gate in the IDT, a task switch results. Handling an interrupt with a separate task offers two advantages:

3. The entire context is saved automatically.

The interrupt handler can be isolated from other tasks by giving it a separate address space, either via its LDT or via its page directory.

4. The actions that the processor takes to perform a task switch . The interrupt task returns to the interrupted task by executing an IRET instruction.If the task switch is caused by an exception that has an error code, the processor automatically pushes the error code onto the stack that corresponds to the privilege level of the first instruction to be executed in the interrupt task.

5. When interrupt tasks are used in an operating system for the 80386, there are actually two schedulers: the software scheduler (part of the operating system) and the hardware scheduler (part of the processor's interrupt mechanism).

6. The design of the software scheduler should account for the fact that the hardware scheduler may dispatch an interrupt task whenever interrupts are enabled.

Key takeaways

1. Just as a CALL instruction can call either a procedure or a task, so an interrupt or exception can "call" an interrupt handler that is either a procedure or a task.
2. The offset field of the gate points to the beginning of the interrupt or exception handling procedure.
3. An interrupt pushes the EFLAGS register onto the stack before the pointer to the interrupted instruction.
4. The IRET instruction is used to exit from an interrupt procedure. IRET is similar to RET except that IRET increments ESP by an extra four bytes (because of the flags on the stack) and moves the saved flags into the EFLAGS register.
5. Interrupts that vector through either interrupt gates or trap gates cause TF (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS.
6. An interrupt that vectors through an interrupt gate resets IF, thereby preventing other interrupts from interfering with the current interrupt handler
7. The privilege rule that governs interrupt procedures is similar to that for procedure calls: the CPU does not permit an interrupt to transfer control to a procedure in a segment of lesser privilege (numerically greater privilege level) than the current privilege level.
8. A task gate in the IDT points indirectly to a task,  The selector of the gate points to a TSS descriptor in the GDT.
9. When interrupt tasks are used in an operating system for the 80386, there are actually two schedulers: the software scheduler (part of the operating system) and the hardware scheduler

4.10 Error Code

1. With exceptions that relate to a specific segment, the processor pushes an error code onto the stack of the exception handler (whether procedure or task). The error code has the format.

2.  The format of the error code resembles that of a selector; however, instead of an RPL field, the error code contains two one-bit items

3. The processor sets the EXT bit if an event external to the program caused the exception.

The processor sets the I-bit (IDT-bit) if the index portion of the error code refers to a gate descriptor in the IDT.

4. If the I-bit is not set, the TI bit indicates whether the error code refers to the GDT (value 0) or to the LDT (value 1). The remaining 14 bits are the upper 14 bits of the segment selector involved. In some cases the error code on the stack is null, i.e., all bits in the low-order word are zero.

Key takeaways

1. If the I-bit is not set, the TI bit indicates whether the error code refers to the GDT (value 0) or to the LDT (value 1).
2. If the I-bit is not set, the TI bit indicates whether the error code refers to the GDT (value 0) or to the LDT (value 1). The remaining 14 bits are the upper 14 bits of the segment selector involved.

4.11 Exception Conditions

1. The following sections describe each of the possible exception conditions in detail. Each description classifies the exception as a fault, trap, or abort.

2. This classification provides information needed by systems programmers for restarting the procedure in which the exception occurred:

3. Faults

The CS and EIP values saved when a fault is reported point to the instruction causing the fault.

4. Traps

• The CS and EIP values stored when the trap is reported point to the instruction dynamically after the instruction causing the trap.
• If a trap is detected during an instruction that alters program flow, the reported values of CS and EIP reflect the alteration of program flow. For example, if a trap is detected in a JMP instruction, the CS and EIP values pushed onto the stack point to the target of the JMP, not to the instruction after the JMP.

5. Aborts

• An abort is an exception that permits neither precise location of the instruction causing the exception nor restart of the program that caused the exception.
• Aborts are used to report severe errors, such as hardware errors and inconsistent or illegal values in system tables.

4.11.1 Interrupt 0 -- Divide Error

The divide-error fault occurs during a DIV or an IDIV instruction when the divisor is zero.

4.11.2 Interrupt 1 -- Debug Exceptions

The processor triggers this interrupt for any of a number of conditions; whether the exception is a fault or a trap depends on the condition:

1. Instruction address breakpoint fault.

2. Data address breakpoint trap.

3. General detect fault.

4. Single-step trap.

5. Task-switch breakpoint trap.

The processor does not push an error code for this exception. An exception handler can examine the debug registers to determine which condition caused the exception.

4.11.3 Interrupt 3 -- Breakpoint

1. The INT 3 instruction causes this trap. The INT 3 instruction is one byte long, which makes it easy to replace an opcode in an executable segment with the breakpoint opcode.

2. The operating system or a debugging subsystem can use a data-segment alias for an executable segment to place an INT 3 anywhere it is convenient to arrest normal execution so that some sort of special processing can be performed. Debuggers typically use breakpoints as a way of displaying registers, variables, etc., at crucial points in a task.

4.11.4 Interrupt 4 -- Overflow

1. This trap occurs when the processor encounters an INTO instruction and the OF (overflow) flag is set.

2.  Since signed arithmetic and unsigned arithmetic both use the same arithmetic instructions, the processor cannot determine which is intended and therefore does not cause overflow exceptions automatically.

3.  Instead it merely sets OF when the results, if interpreted as signed numbers, would be out of range. When doing arithmetic on signed operands, careful programmers and compilers either test OF directly or use the INTO instruction.

4.11.5 Interrupt 5 -- Bounds Check

1. This fault occurs when the processor, while executing a BOUND instruction, finds that the operand exceeds the specified limits.

2. A program can use the BOUND instruction to check a signed array index against signed limits defined in a block of memory.

4.11.6 Interrupt 6 -- Invalid Opcode

1. This fault occurs when an invalid opcode is detected by the execution unit. (The exception is not detected until an attempt is made to execute the invalid opcode; i.e., prefetching an invalid opcode does not cause this exception.)

2.  No error code is pushed on the stack. The exception can be handled within the same task.

3. This exception also occurs when the type of operand is invalid for the given opcode. Examples include an intersegment JMP referencing a register operand, or an LES instruction with a register source operand.

4.11.7 Interrupt 7 -- Coprocessor Not Available

1. This exception occurs in either of two conditions:

2. The processor encounters an ESC (escape) instruction, and the EM (emulate) bit ofCR0 (control register zero) is set.

3. The processor encounters either the WAIT instruction or an ESC instruction, and both the MP (monitor coprocessor) and TS (task switched) bits of CR0 are set.

4.11.8 Interrupt 8 -- Double Fault

1. Normally, when the processor detects an exception while trying to invoke the handler for a prior exception, the two exceptions can be handled serially. If, however, the processor cannot handle them serially, it signals the double-fault exception instead.

2.  To determine when two faults are to be signalled as a double fault, the 80386 divides the exceptions into three classes: benign exceptions, contributory exceptions, and page faults.

4.11.9 Interrupt 9 -- Coprocessor Segment Overrun

1. This exception is raised in protected mode if the 80386 detects a page or segment violation while transferring the middle portion of a coprocessor operand to the NPX. This exception is avoidable.

4.11.10 Interrupt 10 -- Invalid TSS

1. Interrupt 10 occurs if during a task switch the new TSS is invalid. A TSS is considered invalid.

2.  An error code is pushed onto the stack to help identify the cause of the fault. The EXT bit indicates whether the exception was caused by a condition outside the control of the program; e.g., an external interrupt via a task gate triggered a switch to an invalid TSS.

3. This fault can occur either in the context of the original task or in the context of the new task. Until the processor has completely verified the presence of the new TSS, the exception occurs in the context of the original task.

4.  Once the existence of the new TSS is verified, the task switch is considered complete; i.e., TR is updated and, if the switch is due to a CALL or interrupt, the backlink of the new TSS is set to the old TSS. Any errors discovered by the processor after this point are handled in the context of the new task.

4.11.11 Interrupt 11 -- Segment Not Present

1. Exception 11 occurs when the processor detects that the present bit of a descriptor is zero. The processor can trigger this fault in any of these cases:

2. While attempting to load the CS, DS, ES, FS, or GS registers; loading the SS register, however, causes a stack fault.

3. While attempting loading the LDT register with an LLDT instruction; loading the LDT register during a task switch operation, however, causes the "invalid TSS" exception.

4. While attempting to use a gate descriptor that is marked not-present.

This fault is restart able. If the exception handler makes the segment present and returns, the interrupted program will resume execution.

4.11.12 Interrupt 12 -- Stack Exception

1. A stack fault occurs in either of two general conditions:

• As a result of a limit violation in any operation that refers to the SS register. This includes stack-oriented instructions such as POP, PUSH, ENTER, and LEAVE, as well as other memory references that implicitly use SS (for example, MOV AX, [BP+6]). ENTER causes this exception when the stack is too small for the indicated local-variable space.
• When attempting to load the SS register with a descriptor that is marked not-present but is otherwise valid. This can occur in a task switch, an interlevel CALL, an interlevel return, an LSS instruction, or a MOV or POP instruction to SS.

2. When the processor detects a stack exception, it pushes an error code onto the stack of the exception handler.

3. If the exception is due to a not-present stack segment or to overflow of the new stack during an interlevel CALL, the error code contains a selector to the segment in question (the exception handler can test the present bit in the descriptor to determine which exception occurred); otherwise the error code is zero.

4.11.13 Interrupt 14 -- Page Fault

1. This exception occurs when paging is enabled (PG=1) and the processor detects one of the following conditions while translating a linear address to a physical address:

2. The page-directory or page-table entry needed for the address translation has zero in its present bit.

3. The current procedure does not have sufficient privilege to access the indicated page.

4.11.14 Interrupt 16 -- Coprocessor Error

1. The 80386 reports this exception when it detects a signal from the 80287 or 80387 on the 80386's ERROR# input pin.

2. The 80386 tests this pin only at the beginning of certain ESC instructions and when it encounters a WAIT instruction while the EM bit of the MSW is zero (no emulation).

Key takeaways

1. The divide-error fault occurs during a DIV or an IDIV instruction when the divisor is zero.
2. The processor does not push an error code for this exception. An exception handler can examine the debug registers to determine which condition caused the exception
3. The operating system or a debugging subsystem can use a data-segment alias for an executable segment to place an INT 3 anywhere it is convenient to arrest normal execution so that some sort of special processing can be performed.
4. Instead it merely sets OF when the results, if interpreted as signed numbers, would be out of range
5. A program can use the BOUND instruction to check a signed array index against signed limits defined in a block of memory.
6. The exception is not detected until an attempt is made to execute the invalid opcode; i.e., prefetching an invalid opcode does not cause this exception.
7. The processor encounters an ESC (escape) instruction, and the EM (emulate) bit ofCR0 (control register zero) is set.
8. If, however, the processor cannot handle them serially, it signals the double-fault exception instead.
9. This exception is raised in protected mode if the 80386 detects a page or segment violation while transferring the middle portion of a coprocessor operand to the NPX. This exception is avoidable
10. This fault can occur either in the context of the original task or in the context of the new task. Until the processor has completely verified the presence of the new TSS, the exception occurs in the context of the original task.
11. While attempting loading the LDT register with an LLDT instruction; loading the LDT register during a task switch operation, however, causes the "invalid TSS" exception.
12. When the processor detects a stack exception, it pushes an error code onto the stack of the exception handler.
13. The page-directory or page-table entry needed for the address translation has zero in its present bit.
14. The 80386 reports this exception when it detects a signal from the 80287 or 80387 on the 80386's ERROR# input pin.

References

1. A.Ray, K.Bhurchandi, ”Advanced Microprocessors and peripherals: Arch, Programming &
2. Interfacing”, Tata McGraw Hill,2004 ISBN 0-07-463841-6
3. Intel 80386 Programmer's Reference Manual 1986, Intel Corporation, Order no.: 231630-011, December 1995.
4. James Turley, “Advanced 80386 Programming Techniques”, McGraw-Hill, ISBN: 10:0078813425, 13: 978-0078813429.