Fig.: PROM architecture A programmable read only memory is a device that includes both the AND plane and OR-plane within a single IC package. Out of these two arrays AND plane is fixed and OR plane is programmable. Figure shows the block diagram view of PROM. In the PROM the AND array will act as a decoder which will decode the address lines. In mask PROM it is necessary to specify the bit pattern to be stored according to the requirements of the circuits. Since PROMs are used in logic designs these are also referred as PLDs.Advantages:1) As no minimization of logic circuits is needed the circuits can be designed easily.
2) It is possible to modify the circuit faster.
3) These are high speed as compared to discrete SSI/MSI circuits.
4) The Cost is lower.Applications:
F1 = AB’C’ + AB’C + ABC’ + ABCon simplifying we get: F1 = AB’ + ACF2 = A’BC + AB’C + ABC
on simplifying we get: F2 = BC + AC
Applications:
Fig.: PAL architecture Implement the following Boolean expression with the help of programmable array logic (PAL)X =AB + AC’Y= AB’ + BC’
Applications:Programmable Array Logic (PAL)
Programmable Logic Array (PLA)
The full form of PAL is programmable array logic
The full form of the PLA is a programmable logic array
The construction of PAL can be done using the programmable collection of AND & OR gates
The construction of PLA can be done using the programmable collection of AND & fixed collection of OR gates.
The availability of PAL is less prolific
The availability of PLA is more
The flexibility of PAL programming is more
The flexibility of PLA is less
The cost of a PAL is expensive
The cost of PLA is middle range
The number of functions implemented in PAL is large
The number of functions implemented in PLA is limited
The speed of PAL is slow
The speed of PLA is high
2.5 CPLD ArchitectureA complex programmable logic device comprises of a group of programmable FBs (functional blocks). The inputs and outputs of these functional blocks are connected together by a GIM (global interconnection matrix). This interconnection matrix is reconfigurable, so that we can modify the contacts between the functional blocks. There will be some input and output blocks that let us to unite CPLD to external world. The architecture of CPLD is shown below.Generally, the programmable FB looks like the array of logic gates, where an array of AND gates can be programmed and OR gates are stable. But, each manufacturer has their way of thinking to design the functional block. A listed o/p can be found by operating the feedback signals attained from the OR gate outputs. 
Fig.: CPLD architecture In CPLD programming, the design is first coded in Verilog or VHDL language once the code is (simulated and synthesized. During synthesis, the CPLD model (target device) is handpicked and a technology based mapping net list is produced. This list can be close-fitting to the genuine CPLD architecture using a place and route process, typically achieved by the place-and-route software of CPLD Company’s proprietary. Then the operator will do some confirmation processes. If everything is good, he will utilize the CPLD, else he will rearrange it. Features
Applications
Fig.: FPGA architecture An individual CLB is made up of several logic blocks. A lookup table (LUT) is a characteristic feature of an FPGA. An LUT stores a predefined list of logic outputs for any combination of inputs: LUTs with four to six input bits are widely used. Standard logic functions such as multiplexers (mux), full adders (FAs) and flip-flops are also common.The number and arrangement of components in the CLB varies by device. It contains two three-input LUTs an FA and a D-type flip-flop plus a standard mux and two muxes, that are configured during FPGA programming.This simplified CLB has two modes of operation. In normal mode, the LUTs are combined with Mux 2 to form a four-input LUT; in arithmetic mode, the LUT outputs are fed as inputs to the FA together with a carry input from another CLB. Current-generation FPGAs include more complex CLBs capable of multiple operations with a single block; CLBs can combine for more complex operations such as multipliers, registers, counters and even digital signal processing (DSP) functions. Features
ApplicationsIt has applications in image processing, artificial intelligence (AI), data center hardware accelerators, enterprise networking and automotive advanced driver assistance systems (ADAS). Compare CPLD and FPGA CPLD FPGA1
Instant-on. CPLDs start working as soon as they are powered up
Since FPGA has to load configuration data from external ROM and setup the fabric before it can start functioning, there is a time delay between power ON and FPGA starts working. The time delay can be as large as several tens of milliseconds.
2
Non-volatile. CPLDs remain programmed, and retain their circuit after powering down. FPGAs go blank as soon as powered-off.
FPGAs uses SRAM based configuration storage. The contents of the memory is lost as soon as power is disconnected.
3
Deterministic Timing Analysis. Since CPLDs are comparatively simpler to FPGAs, and the number of interconnects are less, the timing analysis can be done much more easily.
Size and complexity of FPGA logic can be humongous compared to CPLDs. This opens up the possibility less deterministic signal routing and thus causing complicated timing scenarios. Thankfully implementation tools provided by FPGA vendors have mechanisms to assist achieving deterministic timing. But additional steps by the user is usually necessary to achieve this.
4
Lower idle power consumption. Newer CPLDs such as CoolRunner-II use around 50 uA in idle conditions.
Relatively higher idle power consumption.
5
Might be cheaper for implementing simpler circuits
FPGAs are much more capable compared to CPLDs but can be more expensive as well.
6
More "secure" due to design storage within built in non-volatile memory.
FPGAs that use external memory can expose the IP externally. Many FPGA vendors offer mechanisms such as encryption to combat this. Design specific protection mechanisms also can be implemented.
7
Very small amount of logic resources.
Massive amount logic and storage elements, with which incredibly complex circuits can be designed. FPGAs have thousands times more resources! This point alone makes FPGAs more popular than CPLDs.
8
No on-die hard IPs available to offload processing from the logic fabric.
Variety of on-die dedicated hardware such as Block RAM, DSP blocks, PLL, DCMs, Memory Controllers, Multi-Gigabit Transceivers etc give immense flexibility. This is not even thinkable with CPLDs.
9
Power down and reprogramming is always required in order to modify design functionality.
FPGAs can change their circuit even while running! (Since it is just a matter of updating LUTs with different content) This is called Partial Reconfiguration, and is very useful when FPGAs need to keep running a design and at the same time update the it with different design as per requirement. This feature is widely used in Accelerated Computing.
Reference Books
