4.1 1 Bit Memory Cell Clocked SR JK MS JK flip flop D and T flipflops

Unit 4

Sequential Logic Design

4.1 1 Bit Memory Cell, Clocked SR, JK, MS J-K flip flop, D and T flip-flops

1 Bit Memory Cell

Latches are basic storage elements that operate with signal levels (rather than signal transitions). Latches controlled by a clock transition are flip-flops. Latches are edge-sensitive devices. Latches are useful for the design of the asynchronous sequential circuit.

J-K Flip Flop:

JK_flip

MS J-K flip flop

It is basically a combination of two JK flip-flops connected together in series.

The first is the “master” and the other is a “slave”.

The output from the master is connected to the two inputs of the slave whose output is fed back to inputs of the master.

In addition to these two flip-flops, the circuit comprises of an inverter.

The inverter is connected to clock pulse in such a way that an inverted clock pulse is given to the slave flip-flop.

In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and vice versa.

Fig. Master Slave Flip flop

Working of a master slave flip flop –

When the clock pulse goes high, the slave is isolated; J and K inputs can affect the state of the system. The slave flip-flop is isolated when the CP goes low. When the CP goes back to 0, information is transmitted from the master flip-flop to the slave flip-flop and output is obtained.

The master flip flop is positive level triggered and the slave flip flop is negative level triggered, hence the master responds prior to the slave.

If J=0 and K=1, Q’ = 1 then the master goes to the K input of the slave and the clock forces the slave to reset therefore the slave copies the master.

If J=1 and K=0, Q = 1 then the master goes to the J input of the slave and the Negative transition of the clock sets the slave and thus copy the master.

If J=1 and K=1, the master toggles on the positive transition and the slave toggles on the negative transition of the clock.

If J=0 and K=0, the flip flop becomes disabled and Q remains unchanged.

Timing Diagram of a Master flip flop –

When the CP = 1 then the output of master is high and remains high till CP = 0 because the state is stored.

Now the output of master becomes low when the clock CP = 1 and remains low until the clock becomes high again.

Thus toggling takes place for a clock cycle.

When the CP = 1 then the master is operational but not the slave.

When the clock is low, the slave becomes operational and remains high until the clock again becomes low.

Toggling takes place during the whole process since the output changes once in a cycle.

This makes the Master-Slave J-K flip flop a Synchronous device which passes data with the clock signal.

D Flip Flop:

D- logic diag
D flip flop

T Flip Flop:

T- logic diag

4.2 Use of preset and clear terminals, hold and setup time, and metastability.

Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q) regardless of clock input status. These inputs are called the preset (PRE) and clear (CLR). The preset input drives the flip-flop to a set state while the clear input drives it to a reset state.

Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable. Violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. In the figure below Tsu is the setup time and Th is the hold time. Whenever the input signal D does not meet the Tsu and Th of the given D flip-flop, metastability occurs.

4.3 Excitation Table for a flip flop, Conversion of flip flops, Typical data sheet specifications of Flip flop application of Flip flops.

EXCITATION TABLE:

flip_1

Conversion for flip flops:

i) SR To JK FlipFlop

flip_2

Excitation Functions:
flip_3

ii) Convert SR To D FlipFlop:

flip_4

Excitation Functions:
S = D
R = D‘
flip_5

4.4 Registers, Shift registers, Counters (ring counters, twisted ring counters), ripple counters, Mod-n counters, up/down counters, synchronous counters, lockout, Clock Skew, Clock jitter.

Registers

Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and it is capable of storing an n-bit word.

Shift registers

Flip flops are used to store one bit of binary data (1or 0).

If we need to store multiple bits of data, we use multiple flip flops.

N flip flops are connected to store n bits of data.

A Register is a device that stores such information. It is a group of flip flops connected in series which is used to store multiple bits of data.

The information stored in these registers can be transferred with the help of shift registers.

This register is a group of flip flops used to store multiple bits of data.

The bits stored in these registers can be moved in/out of the registers by applying clock pulses.

The registers which shift the bits towards left are called “Shift left registers”.
The registers which shift the bits towards the right are called “Shift right registers”.

Shift registers are of 4 types and they are:

Serial In Serial Out register

Serial In the parallel Out register

Parallel In Serial Out register

Parallel In the parallel Out register

Serial-In Serial-Out Shift Register (SISO) –

It allows serial input i.e. one bit after another and produces a serial output is known as Serial-In Serial-Out shift register.

Since it has one output, the data leaves the register one bit at a time in a serial pattern, hence known as Serial-In Serial-Out Shift Register.

The logic circuit is given underneath.

The circuit comprises four D flip-flops which are connected serially.

All these flip-flops are synchronous in nature

Fig. SISO

Serial-In Parallel-Out shift Register (SIPO) –

It allows serial input through a single data line and produces a parallel output.

The logic circuit is given underneath.

The circuit consists of four D flip-flops which are connected synchronously.

The clear (CLR) signal is also connected to all the 4 flip flops in order to RESET them.

The output of the first flip flop is sent to the input of the next and so on.

Fig. SIPO

They are used in communication lines because the main use of the SIPO register is to convert serial data into parallel data.

Parallel-In Serial-Out Shift Register (PISO) –

It allows parallel input data and produces a serial output.

The logic circuit is given underneath.

The circuit comprises four D flip-flops which are connected synchronously.

The clock is connected to all the flip flops but the input data is connected to each flip flop individually through a multiplexer.

The output of the previous flip flop and parallel data input are connected to the input of the MUX and the output of MUX is connected to the next flip flop.

Fig. PISO

It used to convert parallel data to serial data.

Parallel-In Parallel-Out Shift Register (PIPO) –

It allows parallel input data and produces a parallel output.

The logic circuit is given underneath.

The circuit comprises four D flip-flops which are connected synchronously.

The clear (CLR) and clock signals are connected to all flip flops.

In this, there are no interconnections between flip-flops as no serial shifting of the data is required.

Data is provided separately as input for each flip flop and the output is also collected individually from each flip flop.

Fig. PIPO

It is used as a temporary storage device and it acts as a delay element too.

Counters (ring counters, twisted ring counters)

It is a shift register counter whose output of the first flip flop is connected to the second and so on and the output of the last flip flop is fed back to the input of the first flip flop, thus named as a ring counter.

The data pattern in the register circulates as long as clock pulses are applied.

The circuit below comprises of four D flip-flops which are connected synchronously.

The data pattern repeats after every four clock pulses shown in the truth table.

Fig. Ring counter

It is self-decoding.

Hence no extra decoding circuit is required to determine which state the counter is in.

Ripple counters

In this universal clock is not used and only the first flip flop is driven by main clock and the clock input of rest of the following is driven by output of previous flip flops.

Fig. Asynchronous counter

Fig. Timing diagram of Asynchronous counter

It is seen from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is encountered.

Q1 is changing when rising edge of Q0 is encountered and so on.

In this way ripples are generated through Q0,Q1,Q2,Q3 and therefore it is also called as a RIPPLE counter.

Mod-n counters

It counts ten different states and then reset to its initial states.

A simple decade counter will count from 0 to 9 but the decade counters which can go through any ten states between 0 to 15(for 4 bit counter) can also be made.

Truth table is as follows:

Clock pulse	Q3	Q2	Q1	Q0
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1
10	0	0	0	0

Fig. Decade counter

In the above circuit diagram we used nand gate for Q3 and Q1 and sending this to clear input line as the binary representation of 10 is—

1010

And Q3 and Q1 are 1 here, if we give NAND of these two bits then counter clears at 10 and again starts from the beginning.

Up/down counters

Both Synchronous and Asynchronous counters are capable of counting “Up” or counting “Down”, but their is another more “Universal” type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters.

Bidirectional counters, also known as Up/Down counters, are capable of counting in either direction through any given count sequence and they can be reversed at any point within their count sequence by using an additional control input as shown below.

The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0).

Generally most bidirectional counter chips can be made to change their count direction either up or down at any point within their counting sequence. This is achieved by using an additional input pin which determines the direction of the count, either Up or Down and the timing diagram gives an example of the counters operation as this Up/Down input changes state.

Nowadays, both up and down counters are incorporated into single IC that is fully programmable to count in both an “Up” and a “Down” direction from any preset value producing a complete Bidirectional Counter chip. Common chips available are the 74HC190 4-bit BCD decade Up/Down counter, the 74F569 is a fully synchronous Up/Down binary counter and the CMOS 4029 4-bit Synchronous Up/Down counter.

bidirectional up down counter

Synchronous Counter

It has one global clock which drives each and every flip flop and hence output changes in parallel.

The advantage of synchronous counter over the asynchronous counter is that it can operate on a higher frequency and it does not have a cumulative delay.

Fig. synchronous counter

digi3

Fig. The timing diagram of the synchronous counter

Lockout

Sometimes a counter may find itself in some unused states, this happen when if next state of some unused state is again some unused one and if by chance the counter happens to find itself in some unused state and never arrives at in used state then this condition is called “Lock Out”.

Solution:

An additional circuit is require to ensure that “lock out” does not occur. The counter should be designed using the next state to be initial state from the unused state.

To avoid lock out condition the unused states are introduced in front of used states from the above state diagram the 1,4,5,6 and 7 is the sequence and unused states are 0,3 and 6 the states are introduced in front of us States 1,4,5 and 7 respectively.

Clock Skew

Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times. The instantaneous difference between the readings of any two clocks is called their skew.

Clock jitter.

Clock jitter is deviation of a clock edge from its ideal location. Understanding clock jitter is very important in applications as it plays a key role in the timing budget in a system. With the increasing system data rates, timing jitter has become critical in system design, as in some instances the system performance limit is determined by the system timing margin. So a good understanding of the timing jitter becomes very important in system design.

4.5 Sequence Generators.

The sequence generators are nothing but a set of digital circuits which are designed to result in a specific bit sequence at their output. There are several ways in which these circuits can be designed including those which are based on multiplexers and flip-flops. Here in this article we deal with the designing of sequence generator using D flip-flops.

As an example, let us consider that we intend to design a circuit which moves through the states 0-1-3-2 before repeating the same pattern. The steps involved during this process are as follows.

At first, we need to determine the number of flip-flops which would be required to achieve our objective. In our example, there are 4 states which are identical to the states of a 2-bit counter except the order in which they transit. From this, we can guess the requirement of flip-flops to be 2 in order to achieve our objective.

The state transition table is shown by the first four columns of Table I in which the first two columns indicate the present states while the next two columns indicate the corresponding next states. For instance, first state in our example is 0 = “00” which leads to the next state 1 = “01”.

Now this state transition table is to be extended so as to include the excitation table of the flip-flop with which we desire to design our circuit. In our case, it is nothing but D flip-flop due to which we have the fifth and the sixth columns of the table representing the excitation table of D flip-flop.

For example, look at the orange shaded row in Table I in which the present and the next states 1 and 0 (respectively) result in D1 to be 0. The same row also shows the case wherein

Present States		Next States		Inputs of D flip-flops
Q1	Q0	Q1+	Q0+	D1	D0
0	0	0	1	0	1
0	1	1	1	1	1
1	1	1	0	1	0
1	0	0	0	0	0

Now its time to derive the Boolean expressions for D1 and D0. This can be done using any kind of simplification technique including K-map. However as our example is quite simple, we can just use the Boolean laws to solve for D1 and D0. Thus

Having known the inputs to either of the D flip-flops, now we can design our sequence generator as shown in this figure.

sequence generator

Reference Books:

1. Anand Kumar, “Fundamentals of Digital Circuits”, Prentice Hall of India, 1st Edition.

2. J. F. Wakerly, “Digital Design- Principles and Practices,”, Pearson, 3rd Edition.

3. M. M. Mano, “Digital Design,” Prentice Hall India.

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