Unit - 3

Unit - 3

Unit - 3

Sequential circuits and systems

Q1) Explain the working of S-R latch.

A1)

SR Latch is a circuit which has:

(i) 2 cross-coupled NOR gate or NAND gate.

(ii) 2 input S for SET and R for RESET.

(iii) 2 output Q and Q’.

Under normal conditions, both the input remains 0.

RS Latch with NAND gates:

Case-1:  When S’=R’=1 or S=R=0 then

If Q = 1, Q = R’ = 1.

If Q = 0, Q = 0 and R’ = 1 respectively.

Case-2: S’=0, R’=1 (S=1, R=0)

As S’=0, Q = 1(SET state).

In 2nd NAND gate, as Q = R’ = 1, Q’=0.

Case-3: S’= 1, R’= 0 (S=0, R=1)

As R’=0, Q’ = 1.

In 1st NAND gate, as Q =S’ = 1, Q=0 (RESET state).

Case-4: S’= R’= 0 (S=R=1)

When S=R=1, both Q = Q’ = 1 which is not allowed.

So, this input condition is prohibited.

The SR Latch using NOR gate is:

Q2) Convert SR To JK Flip Flop

A2)

Excitation Functions:

                          
Q3) What are shift registers? Write its types.

A3)

• Flip flops are used to store one bit of binary data (1or 0).
• If we need to store multiple bits of data, we use multiple flip flops.
• N flip flops are connected to store n bits of data.
• A Register is a device which stores such information. It is a group of flip flops connected in series which is used to store multiple bits of data.
• The information stored in these registers can be transferred with the help of shift registers.
• This register is a group of flip flops used to store multiple bits of data.
• The bits stored in these registers can be moved in/out of the registers by applying clock pulses.
• The registers which shift the bits towards left are called “Shift left registers”.
  The registers which shift the bits towards right are called “Shift right registers”.

Shift registers are of 4 types and they are:

1. Serial In Serial Out register
2. Serial In parallel Out register
3. Parallel In Serial Out register
4. Parallel In parallel Out register

Q3) Draw and explain ring counter in detail.

A4)

• It is a shift register counter whose output of the first flip flop is connected to the second and so on and the output of the last flip flop is fed back to the input of the first flip flop, thus named as ring counter.
• The data pattern in the register circulates as long as clock pulses are applied.
• The circuit below comprises of four D flip-flops which are connected synchronously.
• The data pattern repeats after every four clock pulses shown in the truth table.

Fig. Ring counter

Q4) What are the steps to design non-overlapping 101 Mealy sequence detector?

A5)

Step 1: Development of the state diagram –

The state diagram of a Mealy machine for a 101-sequence detector is:

Step 2: Assignment of the code–

Rule 1: States having the same next states for a given input condition should have adjacent assignments.

Rule 2: States that are the next states to a single state must be given adjacent assignments.
Rule 1 given preference over Rule 2.

The state diagram after the code assignment is:

Step 3: Making Present State/Next State table –

Step 4: Draw K-maps for Dx, Dy and output (Z) –

Step 5: Final implementation of the circuit –

This is the desired circuit for a Mealy 101 non overlapping sequence detector.

Q5) Name some of the applications of counter.

A6)

• A Counter stores the number of times a particular event or process has occurred in relationship to a clock signal. 
• They are used in digital electronics for counting purpose.
• They can count specific event happening how many times in the circuit.
• For example, in UP counter count increases for every rising edge of clock.
• A counter can follow certain sequence based on our design like any sequence 0,1,3,2… .
• They can be designed with the help of flip flops.

Q6) Explain asynchronous counters.

A7)

• In this universal clock is not used and only the first flip flop is driven by main clock and the clock input of rest of the following is driven by output of previous flip flops.          

Fig. Asynchronous counter

Fig. Timing diagram of Asynchronous counter

• It is seen from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is encountered.
• Q1 is changing when rising edge of Q0 is encountered and so on.

In this way ripples are generated through Q0,Q1,Q2,Q3  and therefore  it is also called  as a RIPPLE counter.

Q7) Explain sequence generator with examples.

A8)

• It is a sequential state machine which takes an input string of bits and generates an output 1 whenever the target sequence has been detected.
• In a Mealy machine, output depends on the present state and the external input (x).
• Hence the output is written outside the states, along with inputs.
• Sequence detector is of two types:

1. Overlapping
2. Non-Overlapping

• In an overlapping sequence detector the last bit of a sequence becomes the first bit of next one.
• In non-overlapping sequence detector the last bit of one sequence does not become the first bit of next one.
• Examples:

                For non-overlapping case

                Input :0110101011001

                Output:0000100010000

For overlapping case

                 Input :0110101011001

                Output:0000101010000

Q8) Convert SR To D Flipflop.

A9)

Excitation Functions:

S = D

R = D‘

Q9) Explain master slave flipflop with timing diagram.

A10)

1. When the clock pulse goes high, the slave is isolated; J and K inputs can affect the state of the system. The slave flip-flop is isolated when the CP goes low. When the CP goes back to 0, information is transmitted from the master flip-flop to the slave flip-flop and output is obtained.
2. The master flip flop is positive level triggered and the slave flip flop is negative level triggered, hence the master responds prior to the slave.
3. If J=0 and K=1, Q’ = 1 then the master goes to the K input of the slave and the clock forces the slave to reset therefore the slave copies the master.
4. If J=1 and K=0, Q = 1 then the master goes to the J input of the slave and the Negative transition of the clock sets the slave and thus copy the master.
5. If J=1 and K=1, the master toggles on the positive transition and the slave toggles on the negative transition of the clock.
6. If J=0 and K=0, the flip flop becomes disabled and Q remains unchanged.

Timing Diagram of a Master flip flop –

1. When the CP = 1 then the output of master is high and remains high till  CP = 0 because the state is stored.
2. Now the output of master becomes low when the clock CP = 1 and remains low until the clock becomes high again.
3. Thus toggling takes place for a clock cycle.
4. When the CP = 1 then the master is operational but not the slave.
5. When the clock is low, the slave becomes operational and remains high until the clock again becomes low.
6. Toggling takes place during the whole process since the output changes once in a cycle.
7. This makes the Master-Slave J-K flip flop a Synchronous device which passes data with the clock signal.