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DSD

Unit - 2

Combinational Logic Design

Q1) Convert the Boolean function into Standard SoP form.

f = p’qr + pq’r + pqr’ + pqr

A1)

Step 1 – By using the Boolean postulate, x + x = x and also writing the last term pqr two more times we get

⇒ f = p’qr + pq’r + pqr’ + pqr + pqr + pqr

Step 2 – By Using Distributive law for 1st and 4th terms, 2nd and 5th terms, 3rdand 6th terms.

⇒ f = qr (p’ + p) + pr (q’ + q) + pq (r’ + r)

Step 3 – Then Using Boolean postulate, x + x’ = 1 we get

⇒ f = qr (1) + pr (1) + pq (1)

Step 4 – hence using Boolean postulate, x.1 = x we get

⇒ f = qr + pr + pq

⇒ f = pq + qr + pr

This is the required Boolean function.

Q2) Convert the Boolean function into Standard PoS form.

f = (p + q + r). (p + q + r’). (p + q’ + r). (p’ + q + r)

A2)

Step 1 – By using the Boolean postulate, x.x = x and writing the first term p+q+r two more times we get

⇒ f = (p + q + r). (p + q + r). (p + q + r). (p + q + r’). (p +q’ + r). (p’ + q + r)

Step 2 – Now by using Distributive law, x + (y.z) = (x + y). (x + z) for 1st and 4thparenthesis, 2nd and 5th parenthesis, 3rd and 6th parenthesis.

⇒ f = (p + q + rr’). (p + r + qq’). (q + r + pp’)

Step 3 − Applying Boolean postulate, x.x’=0 for simplifying of the terms present in each parenthesis.

⇒ f = (p + q + 0). (p + r + 0). (q + r + 0)

Step 4 − Using Boolean postulate, x + 0 = x we get

⇒ f = (p + q). (p + r). (q + r)

⇒ f = (p + q). (q + r). (p + r)

This is the simplified Boolean function.

Hence, both Standard SoP and Standard PoS forms are Dual to one another.

Q3) What is a combinational circuit?

A3) A Combinational circuit is a circuit in which we combine the different gates. For example, encoder, decoder, multiplexer, demultiplexer etc. Some of the characteristics are as follows −

The output of combinational circuit depends only on the levels present at input terminals at any instant of time.

It does not use any memory element. Therefore, the previous state of input does not have any effect on the present state of the circuit.

It can have n number of inputs and m number of outputs.

Block diagram

Block Diagram of combinational circuit

Fig. 1: Combinational circuit (ref.2)

Q4) Simplify f (X, Y, Z) =∏M (0,1,2,4) f (X, Y, Z) =∏M (0,1,2,4) using K-map.

A4)

Prime Implicants ungrouped

Therefore, the simplified Boolean function is

f = (X + Y). (Y + Z). (Z + X)

Q5) Simplify: F (P, Q, R, S) =∑ (0,2,5,7,8,10,13,15)

A5)

F = P’Q’R’S’ + PQ’R’S’ + P’Q’RS’ +PQ’RS’ + QS

F = P’Q’S’ + PQ’S’ + QS

F = Q’S’ +QS

Q6) Simplify: F (A, B, C) =π (0,3,6,7)

A6)

F = A’BC +ABC +A’B’C’ +ABC’

F = BC + C’ (A’B’ + AB)

Q7) Explain half adder with truth table and logic diagram?

A7)

It is a combinational circuit which has two inputs and two outputs.

It is designed to add two single bit binary number A and B.

It has two outputs carry and sum.

Block diagram

Block Diagram of Half Adder

Fig.2: Half adder (ref. 2)

Truth Table

Half Adder Truth Table

Circuit Diagram

Half Adder Circuit Diagram

Fig.3: Half adder

Q8) Explain 4-bit parallel adder?

A8)

Here, A0 and B0 represent the LSB of the four-bit words A and B.

Hence Adder-0 is the lowest stage.

Cin is considered 0.

The rest of the connections are same as that of n-bit parallel adder.

It is a very common logic circuit.

Block diagram

Block Diagram of Four bit Adder

Fig.4: 4-bit parallel adder

Q9) Explain the internal diagram of look ahead carry adder?

A 9) In this, for each adder block, the two bits that are to be added are available instantly.

However, each of them waits for the carry to arrive from the previous one.

So, it is impossible to generate the sum and carry of any block until the input carry is known.

The block waits for the previous block to produce its carry. So, there will be a considerable time delay which is known as carry propagation delay.

Fig 5: Look ahead Carry adder (ref. 2)

Here, the sum is produced by the corresponding full adder as soon as the input signals are applied to it. The carry must propagate to all the stages so that output and carry settle their final steady-state value.

The propagation time is equal to the propagation delay of each adder block, multiplied by the number of adder blocks in the circuit.

It reduces the propagation delay by introducing more complex hardware.

The ripple carry design is suitably transformed in such a way that the carry logic over fixed groups of bits is reduced to two-level logic.

Fig.6: Look ahead Carry adder (ref. 2)

Q10) What are line decoders explain?

A10)

It works as an inverse of an encoder.

It is a combinational circuit which converts n input lines into 2n output lines.

Taking an example of 3-to-8-line decoder.

Truth Table –

X	Y	Z	D0	D1	D2	D3	D4	D5	D6	D7
0	0	0	1	0	0	0	0	0	0	0
0	0	1	0	1	0	0	0	0	0	0
0	1	0	0	0	1	0	0	0	0	0
0	1	1	0	0	0	1	0	0	0	0
1	0	0	0	0	0	0	1	0	0	0
1	0	1	0	0	0	0	0	1	0	0
1	1	0	0	0	0	0	0	0	1	0
1	1	1	0	0	0	0	0	0	0	1

Implementation

D0 is high when X = 0, Y = 0 and Z = 0. Hence,

D0 = X’ Y’ Z’

Similarly,

D1 = X’ Y’ Z

D2 = X’ Y Z’

D3 = X’ Y Z

D4 = X Y’ Z’

D5 = X Y’ Z

D6 = X Y Z’

D7 = X Y Z

Hence,

Fig 7 Decoder

Q11) Explain the implementation of encoder?

A11)

It is a combinational circuit that converts binary information in the form of a 2N input lines into N output lines, which represent N bit code for the input.

For simple encoders, only one input line is active at a time.

For example: Octal to Binary encoder takes 8 input lines and generates 3 output lines.

Fig.8: 8X3 Encoder (ref. 2)

Truth Table –

D7	D6	D5	D4	D3	D2	D1	D0	X	Y	Z
0	0	0	0	0	0	0	1	0	0	0
0	0	0	0	0	0	1	0	0	0	1
0	0	0	0	0	1	0	0	0	1	0
0	0	0	0	1	0	0	0	0	1	1
0	0	0	1	0	0	0	0	1	0	0
0	0	1	0	0	0	0	0	1	0	1
0	1	0	0	0	0	0	0	1	1	0
1	0	0	0	0	0	0	0	1	1	1

From the above truth table, it is seen that the output is 000 when D0 is active; 001 when D1 is active; 010 when D2 is active and so on.

Implementation –

From the above truth table, the output Z is active when the input octal digit is 1, 3, 5 or 7.

Y is active when input octal digit is 2, 3, 6 or 7 and X is active when input octal digits 4, 5, 6 or 7.

Hence, the Boolean functions would be:

X = D4 + D5 + D6 + D7

Y = D2 +D3 + D6 + D7

Z = D1 + D3 + D5 + D7

Hence, the encoder is realised with OR gates as follows:

Fig 9: 8:3 encoder

Limitation of the encoder is that only one input is active at a time.

If more than one input is active, then the output of encoder is undefined.

For example, if D6 and D3 are both active, then, our output would be 111 which is the output for D7.

Problem arises when all inputs are 0.

The encoder gives output 000 which actually is the output for D0. To avoid this, an extra bit is added to the output which is called the valid bit whose value is 0 when all inputs are 0 or 1.

Q12) Explain the logic diagram of multiplexer?

A12)

It is a special type of combinational circuit.

It has n-data inputs, one output and m inputs select lines with 2m = n.

It selects one of the n data inputs and routes it to the output.

The selection of one of the inputs is done by the select lines.

Depending on the code applied at the inputs, one of the n data sources is selected and transmitted to the single output Y.

E is the enable input which is useful for cascading purpose.

It is an active low terminal hence performs the required operation when it is low.