undefined | unit 3 architecture of 8086 microprocessor

Unit-3Architecture of 8086 microprocessorQ1) Write an ALP for reading and displaying a character.A1)

LABEL	CODE	COMMENT
	MOV AH, 1H	keyboard input subprogram
	INT 21H	character input
		character is stored in AL
	MOV C, AL	copy character from AL to C

Q2) Write an ALP to add subtract multiply and divide two numbers.A2)

LABEL	CODE	COMMENT
	ORG0000H
	MOV DX, #07H	move the value 7 to the register AX
	MOV AX, #09H	move the value 9 to accumulator AX
	ADD AX, 00H	add CX value with R0 value and stores the result in AX

	ORG5000H
	MOV BX, #07H	move the value 7 to the register BX
	MOV DX, #09H	move the value 9 to accumulator DX
	MUL DX, 00H	Multiply DX value with R0 value and stores the result in DX

	ORG8000H
	MOV BX, #07H	move the value 7 to the register BX
	MOV AX, #08H	move the value 8 to accumulator AX
	SUBB AX, 09H	Result value is stored in the Accumulator AX

	ORG2000H
	MOV BX, #07H	move the value 7 to the register BX
	MOV AX, #18H	move the value 18 to accumulator AX
	DIV AX, 09H	Final value is stored in the Accumulator AX
	HLT

Q3) Write an ALP to divide a 16 bit number by an 8 bit number.A3)

LABEL	CODE	COMMENT
	MOV SI, 600	assigns 600 to SI
	MOV DI, 500	assigns 500 to DI
	MOV BL, [SI]	moves the content of [SI] to BL register i.e. value of divisor will be stored in BL
	INC SI	increment the content of SI by 1
	MOV AX, [SI]	moves the content of [SI] and [SI + 1] to AX register i.e. value of dividend will be stored in AX
	DIV BL	divide the content of AX by BL, after execution of this instruction the quotient get stored in AL and remainder in AH
	MOV [DI], AX	moves the content of AX to [DI]
	HLT	stops the execution of program

Q4) Write an ALP to find the factorial of a number.A4)

LABEL	CODE	COMMENT
	MOV CX, [5000]	loads 5000 Memory location content to CX Register
	MOV AX, 0001	loads AX register with 0001
	MOV DX, 0000	loads DX register with 0000
	MUL CX	multiply AX with CX and store result in DX:AX pair
	LOOP 040A	runs loop till CX not equal to Zero
	MOV [6000], AX	store AX register content to memory location 6000
	MOV [6001], DX	store DX register content to memory location 6001
	HLT	stops the execution of program

Q5) Write an ALP to find the highest among the given numbers.A5)

LABEL	CODE	COMMENT
DATA	DB 50,44,80,98,42	12H, 2CH, 50H, 62H, 2AH
	MOV CX, 5	Set up loop counter
	MOV BX, OFFSET DATA	BX points to the given data
	SUB AL, AL	AL holds the highest number found till now
AGAIN	CMP AL, [BX]	Compare the next number
	JA NEXT	Jump if AL is still the highest
	MOV AL, [BX]	Else hold the new number
NEXT	INC BX	Points the next number
	LOOP AGAIN	Continue to search
	HLT	stops the execution of program

Q6) Write an ALP to reverse a 16 bit number.A6)

LABEL	CODE	COMMENT
	MOV AL, [3050]	loads contents of memory location 3050 in AL
	MOV AH, [3051]	loads contents of memory location 3051 in AH
	MOV CX, 0004	assign 0004 to CX register pair
	ROL AL, CX	rotate the content of AL register left by 4 bits i.e. value of CX register pair
	ROL AH, CX	rotate the content of AH register left by 4 bits i.e. value of CX register pair
	MOV [3050], AH	stores the content of AH in 3050 memory address
	MOV [3051], AL	stores the content of AL in 3051 memory address
	HLT	stops the execution of program

Q7) Explain the hardware interrupts?A7) NMI (Non mask-able interrupt)-

This is a non-mask-able, edge triggered, high priority interrupt.

On receiving this, the microprocessor executes INT instruction.

Microprocessor obtains the ISR address from location 2 x 4 = 00008H from the IVT.

It reads 4 locations starting from this address to get the values for IP and CS to execute the ISR.

INTR-

This is a mask-able, level triggered, low priority interrupt.

On receiving an interrupt on INTR line, the microprocessor executes 2 INTA pulses.

It is masked by making IF = 0 by software through CLI instruction.

It is unmasked by making IF = 1 by software through STI instruction..

Interrupt processing and pre-defined interruptsThe first five interrupt types are reserved for specific functions.

INT 0 (Divide Error)-

This interrupt occurs whenever there is division error. This condition normally occurs when the divisor is very small as compared to the dividend or the divisor is zero.
Its ISR address is stored at location 0 x 4 = 00000H in the IVT.

INT 1 (Single Step)-

The microprocessor executes this interrupt after every instruction if the TF is set.
Its ISR displays contents for all registers. Its ISR address is stored at location 1 x 4 = 00004H in the IVT.

INT 2 (Non mask-able Interrupt)-

The microprocessor executes this ISR in response to an interrupt on the NMI (Non mask-able Interrupt) line.
Its ISR address is stored at location 2 x 4 = 00008H in the IVT.

INT 3 (Breakpoint Interrupt)-

This interrupt causes breakpoints in the program. It occurs by writing the instruction INT 03H or simply INT.
It is useful in debugging large programs.
Its ISR is used to display the contents of all registers on the screen. Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.

INT 4 (Overflow Interrupt)-

It occurs if the overflow flag is set and the microprocessor executes the INTO (Interrupt on Overflow) instruction.
It detects overflow error in signed arithmetic operations.
Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

Q8) Explain the BIU?A8)

It is a 16 bit bidirectional data bus and 20 bit address bus.

 It is responsible for all external bus operations. It performs the following functions namely Instruction fetching, Instruction queuing, Operand fetching and storage, address relocation and bus control.

It uses a mechanism called as an instruction stream queue for implementation of a pipeline architecture.

This queue permits pre fetching of up to six bytes of instruction code. Whenever the queue is not full, it has room for at least two more bytes. It is free to look ahead in the program by pre fetching the next sequential instruction.

These pre fetched instructions are held in its FIFO queue. It fetches two instruction bytes in a single memory cycle.

It shifts automatically through the FIFO to the empty location after a byte is loaded at the input end of the queue.

The EU accesses the queue from the output end. It reads instruction byte one by one from the output of the queue. If the queue is full, the EU does not request access to operand in memory. These intervals are known as Idle state.

When the EU request it to read or write operands from memory or I/O, the BIU is already in the process of fetching an instruction, then it first completes the instruction fetch cycle before the operand read / write cycle is initiated.

It comprises of a dedicated adder which generates the 20 bit physical address that is output on the address bus.

For example: The physical address to be fetched is formed by combining the current contents of the CS register and the IP register.

Q9) Write types of memory segmentation and rules of segmentation?A9) Types of Segmentation –

Overlapping Segment – A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another segment starts along with this 64kilobytes location of the first segment, then the two are said to be Overlapping Segment.

Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go up to 64kilobytes. But if another segment starts before this 64kilobytes location of the first segment, then the two segments are said to be Non-Overlapped Segment.

Rules of Segmentation Segmentation process follows some rules as follows:

The starting address of a segment should be such that it can be evenly divided by 16.

Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Q10) Explain the register organization of 8086?A10)

The 8086 microprocessor has a total of fourteen registers that can be used by the programmer.

It is basically divided into four groups.

Four General purpose registers Four Index/Pointer registers Four Segment registers Two Other registers

Accumulator register consists of two 8-bit registers AL and AH. They can be used together as a 16-bit register AX. AL contains the lower order byte and AH contains the higher order byte. Accumulator can be used for both I/O operations and string manipulation.

Base register comprises of two 8-bit registers BL and BH. They can be used together as a 16-bit register BX. BL contains the low-order byte and BH contains the high-order byte. BX register contains a data pointer used for base, base index or register indirect addressing.

Count register comprises of two 8-bit registers CL and CH. They can be used together as a 16-bit register CX. CL register contains the low order byte and CH contains the high-order byte. It is used in Loop, shift/rotate instructions and also as a counter in string manipulation.

Data register comprises of two 8-bit registers DL and DH. They can be used together as a 16-bit register DX. DL register contains the low order byte and DH contains the high-order byte. They can be used as a port number in I/O operations. In integer 32-bit multiplication and division instruction, the DX register contains higher order word of the resulting number.

Fig.1: General purpose registers

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