undefined | unit 4 assembly language programming based on intel 8085

Unit-4Assembly Language Programming based on Intel 8085/8086 Q1) Write a program to add two 8-bit numbers.A1)

MEMORY ADDRESS	MNEMONICS	COMMENTS
3000	LDA 3050
3003	MOV H, A	A -> H
3004	LDA 3051	A<-[2051]
3007	ADD H	A + H -> A
3006	MOV L, A	A -> L
3007	MVI A 00	00 -> A
3009	ADC A	A+A+carry -> A
300A	MOV H, A	A -> H
300B	SHLD 4050	H→4051, L→4050
300E	HLT

Explanation:

LDA 3050 moves the contents of 3050 memory location to the accumulator (A).

MOV H, A copies contents of accumulator to register H .

LDA 3051 moves the contents of 3051 memory location to the accumulator.

ADD H adds contents of A and H. The result is then stored in A.

MOV L, A copies contents of A to L.

MVI A 00 moves immediate data (i.e., 00) to A.

ADC A adds contents of A(00), contents of register specified (i.e A) and carry (1).

MOV H, A copies contents of A (01) to H.

SHLD 4050 moves the contents of L register in 4050 memory location and contents of H register in 4051 memory location.

HLT stops program execution.

Q2) Write a program to subtract two 8-bit numbersA2)

Mnemonics	Operand	Comments
LXI H,	3502 H	Get address of 2nd no. in H-L pair.
MVI A,	99	Place 99 in accumulator.
SUB	M	9’s compliment of 2nd no.
INR	A	10’s compliment of 2nd no.
DCX	H	Get address of 1st no.
ADD	M	Add 1st no. & 10’s compliment 2nd no.
DAA		Decimal Adjustment.
STA	3503 H	Store result in 3503 H.
HLT		Stop the program.

DATA3501- 96 H.3502- 38 H. The result is stored in memory location 3503 H. RESULT2503- 58 H.Q3) Write a program to add two 16-bit numbers.A3)We are taking two numbers ABCD + FE2D = 1B9FAINPUT:

….	…
5000H	CD
5001H	AB
5002H	2D
5003H	FE
…	….

PROGRAM:

Labels	Mnemonics	Operand	Comments
	LXI H,	5000H	Point to LSB of first operand
	LXI D,	5002H	Point to LSB of second address
	LDAX	D	Load Acc with content pointed by DE
	ADD	M	Add memory element pointed by HL with Acc
	MOV C,	A	Store LSB result at C
	INX	H	Point to next byte of first operand
	INX	D	Point to next byte of second operand
	LDAX	D	Load Acc with content pointed by DE
	ADC	M	Add memory element pointed by HL with Acc+ Carry
	MOV B,	A	Store the MSB at B
	MOV H,	B	Move B to H
	MOV L,	C	Move C to L
	SHLD	5050H	Store the result at 5050H and 5051H
	JNC	DONE	Skip to end
	MVI A,	01H	Load 1 to Acc
	STA	5052H	Store Acc content into 5052H
DONE:	HLT		Stop the program.

RESULT:5052: FA5053: B95054: 01Q4 WAP for finding lowest no. in data arrayA4)

Labels	Mnemonics	Operand	Comments
	LXI H,	5000H	Address for count in H-L pair
	MOV C,	M	Count in C register
	INX	H	Address for 1st no.
	MOV A,	M	1st no. sent to the accumulator
	DCR	C	Decrement count
LOOP:	INX	H	Address of next no.
	CMP	M	Compare next no.
	JC	AHEAD	If no, get smaller no. in accumulator go to AHEAD
	MOV A,	M	get smaller no. in accumulator
AHEAD:	DCR	C	Decrement count
	JNZ	LOOP
	STA	4000H	Store in 4000H
	HLT		Stop program

DATA:5000H : 035001H : 755002H : 985003H : 99RESULT:4000H : 03Q5) WAP for finding highest no. in data arrayA5)

Labels	Mnemonics	Operand	Comments
	LXI H,	5000H	Address for count in H-L pair
	MOV C,	M	Count in C register
	INX	H	Address for 1st no.
	MOV A,	M	1st no. sent to the accumulator
	DCR	C	Decrement count
LOOP:	INX	H	Address of next no.
	CMP	M	Compare next no.
	JNC	AHEAD	If no, go to AHEAD
	MOV A,	M	Or get larger no. in accumulator
AHEAD:	DCR	C	Decrement count
	JNC	LOOP
	STA	4000H	Store in 4000H
	HLT		Stop program

DATA:5000H : 035001H : 755002H : 985003H : 99RESULT:4000H : 99Q6) Write a program for delay subroutine using registerA6)

The microprocessor does not execute other tasks, when the delay subroutine is executed.

For the delay, we use the instruction execution times.

Execution of some instructions in a loop, the delay can be generated.

Some methods for generating delays are as follows:

Using NOP instructions

Using 8-bit register as counter

Using 16-bit register pair as counter.

Using NOP instructions

It takes four clock pulses for fetching, decoding and executing.

If the 8085 MPU is working on 4MHz clock frequency, then the internal clock frequency is 2MHz.

Hence, can easily determine that each clock period is 1/2 of a microsecond.

So the NOP will be executed in 1/2 * 4 = 2µs.

If the entire memory uses NOP instruction, then 64K NOP instructions will be executed. Then the overall delay will be 216 * 2µs = 131072µs.

Hence, it can be used to generate a short time delay of few milliseconds.

Using 8-bit register as counter

Labels	Mnemonics	Operand	Comments
	MVI B,	FFH	7 T states required
LOOP:	DCR	B	4 T states required and will be executed 255 (FF) times
	JNZ	LOOP	10 T states required when it jumps (It jumps 254 times), otherwise it take 7 T-States
	RET		10 T states required

7 + ((4*255) + (10*254)) + 7 + 10 = 3584. So the time delay will be 3584 * 1/3µs = 1194.66µs. So when small delay is needed, then we can use this technique with some other values in the place of FF.Using 16-bit register pair as counter

Labels	Mnemonics	Operand	Comments
	LXI B,	FFFFH	10 T states required
LOOP:	DCX	B	6 T states required
	MOV A,	B	4 T states required
	ORA	C	4 T states required
	JNZ	LOOP	10 T states required when it jumps, otherwise it take 7 T-States
	RET		10 T states required

10 + (6 + 4 + 4 + 10) * 65535H – 3 + 10 = 17 + 24 * 65535H = 1572857. Time delay = 1572857 * 1/3µs = 0.52428s. Here we are getting nearly 0.5s delay.Q7) Explain the use and how the memory locations of stack are affected?A7) Stack is set of memory locations which are specified by the programmer in main program. These memory locations are used to store binary information temporarily during execution of program. The stack is shred by programmer and the microprocessor. There is a 16-bit memory address in stack pointer register (SP) of microprocessor. LXI SP, memory address instruction is used to load the SP with specific memory address. The Stack is assigned the highest memory location so that the program is not affected. By using PUSH instruction, the data bytes in the register pair can be stored in the stack in reverse order. Using POP instruction, they can be again transferred to the respective registers. The address in the SP register indicates the next two memory locations which are in descending order can be used for storage.Example-1

LXI SP, xx99H	Load SP register with address xx99
PUSH H	It copies content of register pair (HL) on stack [H:xx98,L:xx97]. The SP register is decremented each time [SP = xx97]
PUSH B	It copies content of register pair (BC) on stack [B:xx96, C:xx95] The SP register is decremented each time [SP = xx95]
PUSH PSW	It is program status word which means content of A and F [A:xx94, F: xx93]. The SP register is decremented each time [SPxx93]
POP H	It copies content of top 2 memory locations to HL. [H: xx94, L: xx93]. The SP is incremented each time [SP: xx95]
POP B	It copies content of top 2 memory locations to HL. [H: xx95, L: xx96]. The SP is incremented each time [SP: xx97]
POP PSW	It is program status word which means content of A and F [A: xx98, F: xx97]. The SP register is incremented each time [SP: xx99]

Q8) How CALL and RETURN instructions are executed in subroutine?A8) It is group of instructions written separately from the main program. We can use this sub program many times in main program by using CALL and RETURN instructions. Example-1

Memory location	Instruction
2000H	LX SP, 2300H
2040H	CALL 2070H
2043H	Next Instruction

The CALL instruction requires 5 machine cycles and 18 T-states. The machine cycles are explained below.M1 Opcode Fetch: The content of program counter 2040 are placed on address bus and the machine code is fetched using data bus. In the same time the program counter is incremented by one. So, now the new value in program counter is 2041H. After instruction is decoded and executed SP is decremented by 1. This machine cycle needs 6T-states.M2-M3: These two are memory read cycles. The 16-bit address of CALL which is 2070H is fetched. The lower order 70H is fetched first and placed in internal register Z. Next the higher order address is fetched which is 20H and placed in register W. For machine cycle M3 the program counter is upgraded to location pointing next instruction. The both machine cycles require 3T states each.M4-M5: It is storing of program counter. When M4 begins the content of SP register 23FFH is placed on address bus. The higher order is placed on the data bus 20H and stored in stack location 23FFH. Then simultaneously the SP is also decremented by 1(23FEH). In M5 the content of SP is placed on address bus and lower byte of program counter 43H is placed on data bus and stored in stack location 23FEH. The both machine cycles require 3T states each. RET ExecutionAt the end of subroutine RET is executed. The program sequence is transferred to 2043H location. This was stored in top two stack locations 23FEH and 23FFH in CALL instruction. The RET requires 3 machine cycles. M1 is the opcade fetch. In M2 content of SP are placed on address bus. The data byte 43H from top of stack is fetched first and stored in Z and SP is incremented by 1. The next byte is copied in M3 i.e 20H and stored in W and SP is again incremented by 1(2400H).Q9) What are conditional and continuous loop?A9) The programming technique used to instruct the microprocessor to repeat task is called looping. The techniques such as counting and indexing are used to set up a loop. The loop can be of two typesContinuous LoopThe loop formed by using unconditional jump instruction. This loop will follow the instructions and repeat the same task until the system is reset.Conditional LoopThe conditional jump instruction set up a conditional loop. These instructions check the flags such as zero, carry etc and then repeat the specified task if that condition is satisfied. These loops include counting and indexing.Indexing means to refer objects with sequential numbers. The counting is set up by loading specific count value in the register. It can be incremental or decremental. Q10) What are instructions and how many instructions are there for 8085?A10) An instruction is a binary pattern designed inside a microprocessor to perform a specific function.

The entire group of instructions that a microprocessor supports is called Instruction Set.

8085 has 246 instructions.

Each instruction is represented by an 8-bit binary value.

These 8-bits of binary value is called Op-Code or Instruction Byte.

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