Unit 3

Q1) A four bit modulo 16 ripple counter uses JK flip flops. If the propagation delay of each flip flop is 50ns, find the maximum clock frequency that can be used?

Sol: Propagation delay of each flip flop = 50ns

Four bit modulo 16 ripple counter represents n=4

Maximum clock frequency = = = 5MHz

Q2) A pulse train with a frequency of 1MHzis counted using a modulo-1024 ripple counter built with JK flip flop. Find the maximum permissible propagation delay/flip flop for proper operation of the counter?

Sol: f= 1MHz

T= 1000ns

Mod-1024= 2n

210=2n

n=10

Propagation delay for one flip flop Td = T/n = 1000x 10-9/10

Td=100ns

Q3) If a counter having 10 flip flops is initially 0. Find the count it will hold after 2060 pulses?

Sol: As counter has 10 flip-flops.

Hence, it counts from (0)10-(1023)10. So, total it has 1024 states.

2060-1024 = 1036

1036-1024 = 12

So, the value of counter after 2060 pulses is same that after 12 pulses given as 1100

(12)10 = (1100)2

So, after 2060 pulses the count will be (1100)2

Q4) A certain JK flip flop has tpd =12ns. Find the largest MOD counter that can be constructed from such flip flops and still operate upto 10MHz?

Sol: output frequency fout =

10x106=

n=8bits

The given counter has 8-bits. It can have maximum count of 256. So, we can construct MOD-256 counter with given information.

Q5) A switch trail ring counter is made by using a single D flip flop. What will be the resulting circuit?

Sol: In a switch trail ring counter is made by using a single D flip flop, the complementary output is connected to D then it becomes T flip flop.

Q6) Explain the pin configuration of 7490?

Sol: This is basically a decade counter which counts upwards on applying the clock signal. It consists of four master-slave JK flip flops as divide by 2 and divide by 5 counters in it. It can store decimal digits in 4-bit binary numbers. The divide by 2 and divide by 5 counters can be used individually each by disabling the other or both simultaneously to produce MOD-10 counter.

                                                              Fig: Pin Diagram of 7490

The pin configuration is explained below.

Pin1: clock input 2

Pin2: reset1

Pin3: reset2

Pin3: Not connected

Pin4: Supply voltage

Pin5: reset3

Pin6: reset4

Pin8: BCD output bit 2 (Qc)

Pin9: BCD output bit 1 (Qb)

Pin10: ground

Pin11: BCD output bit 3 (QD)

Pin12: BCD output bit 0 (QA)

Pin13: Not connected

Pin14: clock input 1

It is 4-bit binary decade counter with four outputs QA, QB, QC, QD. After the count value reaches 10 the binary output is reset. The MOD of this IC can be changed by the reset pins R0(1), R0(2), R9(1) and R9(2). If R0(1), R0(2) is high or R9(1) and R9(2) are ground the four outputs QA, QB, QC, QD are reset to 0000.

Q7) Implement BCD decade counter using 7490?

Sol: The push button switch SW1 when released eery time will increase the count value by one. When the count due to SW1 reaches 1001 the outputs QA, QB, QC, QD are reset to 0000.

Truth table is as follows:

Q8) Explain the internal structure and pin configuration of IC 7474?

Sol:

Pin 1, Clear 1 Input
Pin 2, D1 input
Pin 3, Clock 1 Input
Pin 4, Preset 1 Input
Pin 5, Q1 output
Pin 6, Complement Q1 output
Pin 7, Ground
Pin 8, Complement Q2 output
Pin 9, Q2 output
Pin 10, Preset 2 Input
Pin 11, Clock 2 Input
Pin 12, D2 input
Pin 13, Clear 2 Input
Pin 14, Positive Supply

It is basically a dual D type edge triggered flip flop. The input is high on the positive edge of clock pulse. When the clock pulse is low or high the data in the D flip flop can be changed without changing the output. The input is reset when there is LOW logic level at the preset.

The value stored at particular value of clock cycle becomes the output. After that for different time the value of output does not change. It is widely used in data storage.

Q9) Convert SR to D flip flop?

Sol:

• Excitation Functions:
  S = D
  R = D‘
                               

Q10) List the differences between asynchronous and synchronous counters?

Sol:

Q11) Explain Master slave flip flop?

      Sol: It is a combination of two JK flip-flops connected in series.

      The first is the “master” and the other is a “slave”.

      The output from the master is connected to the two inputs of the slave whose output is fed back to inputs of the master.

      In addition to these two flip-flops, the circuit comprises an inverter.

      The inverter is connected to clock pulse in such a way that an inverted clock pulse is given to the slave flip-flop.

      In other words, if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and vice versa.

                                         Fig.  Master-Slave Flip flop

Working of a master-slave flip flop –

1. When the clock pulse goes high, the slave is isolated; J and K inputs can affect the state of the system. The slave flip-flop is isolated when the CP goes low. When the CP goes back to 0, information is transmitted from the master flip-flop to the slave flip-flop, and output is obtained.
2. The master flip flop is a positive level triggered and the slave flip flop is negative level triggered, hence the master responds before the slave.
3. If J=0 and K=1, Q’ = 1 then the master goes to the K input of the slave and the clock forces the slave to reset therefore the slave copies the master.
4. If J=1 and K=0, Q = 1 then the master goes to the J input of the slave and the Negative transition of the clock sets the slave and thus copy the master.
5. If J=1 and K=1, the master toggles on the positive transition, and the slave toggles on the negative transition of the clock.
6. If J=0 and K=0, the flip flop becomes disabled and Q remains unchanged.

Timing Diagram of a Master flip flop –

1. When the CP = 1 then the output of master is high and remains high till  CP = 0 because the state is stored.
2. Now the output of the master becomes low when the clock CP = 1 and remains low until the clock becomes high again.
3. Thus toggling takes place for a clock cycle.
4. When the CP = 1 then the master is operational but not the slave.
5. When the clock is low, the slave becomes operational and remains high until the clock again becomes low.
6. Toggling takes place during the whole process since the output changes once in a cycle.
7. This makes the Master-Slave J-K flip flop a Synchronous device that passes data with the clock signal.