Processor Architecture
Unit - 6Current trends in processor architecture Q 1) What is mean by ARM and RISK?A 1) ARM processor:An ARM processor is one of a family of CPUs based on the RISC (reduced instruction set computer) architecture developed by Advanced RISC Machines (ARM). ARM makes 32-bit and 64-bit RISC multi-core processors. RISC processors are designed to perform a smaller number of types of computer instructions so that they can operate at a higher speed, performing more millions of instructions per second (MIPS). By stripping out unneeded instructions and optimizing pathways, RISC processors provide outstanding performance at a fraction of the power demand of CISC (complex instruction set computing) devices. ARM processors are extensively used in consumer electronic devices such as smartphones, tablets, multimedia players and other mobile devices, such as wearables. Because of their reduced instruction set, they require fewer transistors, which enables a smaller die size for the integrated circuitry (IC). The ARM processor’s smaller size, reduced complexity and lower power consumption makes them suitable for increasingly miniaturized devices. ARM processor features include: 1 Load/store architecture.2 An orthogonal instruction set.3 Mostly single-cycle execution.4 Enhanced power-saving design.5 64 and 32-bit execution states for scalable high performance.6 Hardware virtualization support. RISCIt is a design philosophy aimed at delivering simple but powerful instruction set that executes within a single cycle at high clock speed. RISC is an acronym for Reduced Instruction Set Computers CISC – Complex Instruction Set Computer The RISC Design Philosophy CISC and RISC differ in complexities of their instruction sets where CISC is more complex than RISC. Concentrates on reducing the complexity of instructions performed by the hardware to provide greater flexibility and intelligence in software. The smaller instruction set allows a designer to implement a hardwired control unit which runs at a higher clock rate than its equivalent micro sequenced control unit. Q 2) Write a four major rules of ARM and RISK?A 2)Four major rules of arm and risk:Instructions– RISC processors have a reduced number of instruction classes. These classes provide simple operations that can each execute in a single cycle. The compiler or programmer synthesizes complicated operations (a divide operation) by combining several simple instructions. Each instruction is a fixed length to allow the pipeline to fetch future instructions before decoding the current instruction. In contrast, in CISC processors the instructions are often of variable size and take many cycles to execute. Pipelines —The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle for maximum throughput. There is no need for an instruction to be executed by a nonprogram called microcode as onCISC processors. Registers—RISC machines have a large general-purpose register set. Any register can contain either data or an address. In contrast, CISC processors have dedicated registers for specific purposes. Load-store architecture—The processor operates on data held in registers. Separate load and store instructions transfer data between the register bank and external memory. In contrast, with a CISC design the data processing operations can act on memory directly. Q 3) Write a short note on version ARM7.A 3)The Arm7™ embedded microcontroller core is a member of the Advanced RISC Machines (Arm®) family of general purpose 32-bit microprocessors, which offer high performance and very lower power consumption. Its outstanding feature is the 16-bit Thumb® subset of the most commonly used 32-bit instructions. These are expanded at run time with no degradation of system performance. This gives 16-bit code density (saving memory area and cost) coupled with 32-bit processor performance. The Arm® architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The Arm memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signal facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs. 
Fig.ARM7 Q 4) Write a short on ARM 9.A 4)The Arm9™ embedded microcontroller core is a member of the Advanced RISC Machines (Arm®) family of general purpose 32-bit microprocessors, which offer high performance and very low power consumption. Its outstanding feature is the 16-bit Thumb® subset of the most commonly used 32 Bit instructions. These are expanded at run time with no degradation of system performance. This gives 16-bit code density (saving memory area and cost) coupled with 32-bit processor performance. The Arm architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip. Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The Arm memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs. 
Fig.ARM9 Q 5) Write a short note on ARM 11. A 5)ARM11 is a group of older 32-bit RISC ARM processor cores licensed by ARM Holdings.[1] The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from 2002 to 2005, they are no longer recommended for new IC designs, instead ARM Cortex-A and ARM Cortex-R cores are preferred. The Arm11 family includes four processors: 1 Arm11MPCore introduced multicore technology and is still used in a wide range of applications.2 Arm1176JZ(F)-S is the highest-performance single-core processor in the Classic Arm family. It also introduced Trust Zone technology to enable secure execution outside of the reach of malicious code.3 Arm1156T2(F)-S is the highest-performance processor in the real-time Classic Arm family.4 Arm1136J(F)-S is very similar to Arm926EJ-S, but includes an extended pipeline, basic SIMD (Single Instruction Multiple Data) instructions, and improved frequency and performance. Q 6) What is the basic feature of ARM11?A 6)ARM11 Processor FeaturesPowerful ARMv6 instruction set architecture. ARM Thumb® instruction set reduces memory bandwidth and size requirements by up to 35%. ARM Jazelle technology for efficient embedded Java execution. SIMD (Single Instruction Multiple Data) media processing extensions deliver up to 2x performance for video processing. Q 7) Write a Advantages and Disadvantages of ARM processor.A 7) Advantages of ARM Processor:Affordable to create – 1 ARM Processor is very affordable as it does not need expensive equipment’s for its creation. 2 When compare to other processors, it is created at much lesser price. 3 This is why they are apt for making of low cost Mobile phones and other electronic devices.Low Power Consumption – 1 AMP Processors have lesser power consumption. They were initially designed for performing at lesser power. 2 They even have lesser transistors in their architecture. They have various other features that allow for this.Work Faster – 1 ARM performs single operation at a time. This makes it work faster. 2 It has lower latency that is quicker response time.Multiprocessing feature – 1 ARM processors are designed so that they can be used in cases of multiprocessing systems where more than one processors are used to process information. 2 First AMP processor introduced by name of ARMv6K had ability to support 4 CPUs along with its hardware.Better Battery Life – 1 ARM Processors have better battery life. This is seen from administering devices that use ARM processors and those that do not.2 Those that used ARM processors worked for longer and got discharged later than those that did not work on ARM processors.Load store architecture – 1 The processor uses load store architecture that stores data in various registers (to reduce memory interactions).2 It has separate load and store instructions that are used to transfer data between external memory and register bank.Simple Circuits – 1 ARM processors have simple circuits; hence they are very compact and can be used in devices that are smaller in size (several devices are becoming smaller and more compact due to customer demands).Disadvantages of ARM Processor :It is not compatible with X86 hence it cannot be used in Windows. The speeds are limited in some processors which might create problems. Scheduling instructions is difficult in case of ARM processors. There must be proper execution of instructions by programmer. This is because entire performance of ARM processors depends upon their execution. ARM Processor needs very highly skilled programmers. This is because of importance and complexity of execution (processor shows lesser performance when not executed properly. Q 8) Write suitability of ARM processor in embedded application.A 8)The ARM instruction set differs from the pure RISC definition in several ways that make the ARM instruction set suitable for embedded applications: Variable cycle execution for certain instructions—Not every ARM instruction executes in a single cycle. For example, load-store-multiple instructions vary in the number of execution cycles depending upon the number of registers being transferred. Inline barrel shifter leading to more complex instructions—The inline barrel shifter is a hardware component that pre-processes one of the input registers before it is used by an instruction. Thumb 16-bit instruction set—ARM enhanced the processor core by adding a second 16-bit instruction set called Thumb that permits the ARM core to execute either 16- or 32-bit instructions. Conditional execution—An instruction is only executed when a specific condition has been satisfied. Enhanced instructions—The enhanced digital signal processor (DSP) instructions were added to the standard ARM instruction set to support fast 16×16-bit multiplier operations and saturation. The ARM processor controls the embedded device. An ARM processor comprises a core plus the surrounding components that interface it with a bus. These components can include memory management and caches. Controllers coordinate important functional blocks of the system. Two commonly found controllers are interrupt controller and memory controller. The peripherals provide all the input-output capability external to the chip and are responsible for the uniqueness of the embedded device. A bus is used to communicate between different parts of the device. Q 9)Explain ARM Bus technology.A 9)ARM Bus Technology Embedded systems use different bus technologies. The most common PC bus technology, the Peripheral Component Interconnect (PCI) bus, this type of technology is external or off-chip. Embedded devices use an on-chip bus that is internal to the chip and that allows different peripheral devices to be interconnected with an ARM core. There are two different classes of devices attached to the bus. •Bus master(ARM processor core)—a logical device capable of initiating a data transfer with another device across the same bus. Bus slaves(Peripherals)—logical devices capable only of responding to a transfer request from a bus master device. A bus has two architecture levels. physical level — that covers the electrical characteristics and bus width (16, 32, or 64 bits). Second level deals with protocol—the logical rules that govern the communication between the processor and a peripheral. Q 10) Explain AMBA BUS protocol.A 10) AMBA Bus ProtocolThe Advanced Microcontroller Bus Architecture (AMBA) has been widely adopted as the on-chip bus architecture used for ARM processors. The first AMBA buses introduced were the 1.ARM System Bus(ASB) and the2. ARM Peripheral Bus(APB). Later ARM introduced another bus design, called the 3. ARM High Performance Bus(AHB). Plug-and-play interface for hardware developers — Using AMBA, peripheral designers can reuse the same design on multiple projects. A peripheral can simply be bolted onto the on-chip bus without having to redesign an interface for each different processor architecture. An embedded system has to have some form of memory to store and execute code. It has some specific specific memory characteristics, such as hierarchy, width, and type. Hierarchy-All computer systems have memory arranged in some form of hierarchy. Memory trade-offs: the fastest memory cache is physically located nearer the ARM processor core and the slowest secondary memory is set further away. Cache is placed between main memory and the core. It is used to speed up data transfer between the processor and main memory. The main memory is around 256 KB to 256 MB, depending on the application. Secondary storage is the largest and slowest form of memory may vary from 600 MB to 60 GB. Width-The memory width is the number of bits the memory returns on each access—typically 8, 16, 32, or 64 bits. Use of thumb instructions —- If you have an uncached system using 32-bit ARM instructions and 16-bit-wide memory chips, then the processor will have to make two memory fetches per instruction. Each fetch requires two 16-bit loads. This obviously has the effect of reducing system performance, but the benefit is that 16-bit memory is less expensive .In contrast, if the core executes 16-bit Thumb instructions, it will achieve better performance with a 16-bit memory. Types-Read-only memory (ROM) is the least flexible of all memory types because it contains an image that is permanently set at production time and cannot be reprogrammed. Many devices also use a ROM to hold boot code. Flash ROM can be 1. Written to as well as read,2. It is slow to write. Its main use is for holding the device firmware. The erasing and writing of flash ROM are completely software controlled.Dynamic random access memory (DRAM) is the most commonly used RAM for devices. It has the lowest cost per megabyte. DRAM is dynamic it needs to have its storage cells refreshed and given a new electronic charge every few milliseconds, so you need to set up a DRAM controller before using the memory. Q 11) Write a features of ARM7 data flow model.A 11) ARM7 DATAFLOW MODELWhen an instruction is decoded inside the ARM core and how a particular instruction is executed by interacting with the internal registers file and then send result out of the registers. 
Fig. ARM7 data flow model Features.1 Von Neuman Architecture Hence data coming through bus is either instruction or data (same memory)..2 The Sign extend hardware converts signed 8-bit & 16-bit numbers to 32-bit values as they are read from memory & placed in a register (for signed values), fill zeros if unsigned..3 Source operands (Rn & Rm) are read from the register file using the internal buses A & B respectively & result Rd is written back..4 The PC value is in the address register which is fed in to the incremented, then the incremented value is copied back in to r15..5 It is also written in to address register to be used as the address for the next instruction fetch..6 ALU: (The Arithmetic & logic Unit) or MAC (multiply & accumulate Unit) takes the register values Rn & Rm from A & B buses & computers a result)..7 Data processing instructions write the result in Rd directly to the register file..8 Load & Store instruction use the ALU to generate on Address to be to be held in the address register & broadcast on the address bus. Q 12) Explain CPSR and SPSR register.A 12 ) CPSR AND SPSR REGISTERCPSR: 1 The CPSR (Current Program Status Register) this stores additional information about the state of the processor.2 And finally, in privileged modes, a particular SPSR (Saved Program Status Register).3 This stores a copy of the previous CPSR value when an exception occurs.SPSR: 1 A Saved Program Status Register (SPSR) stores the current value of the CPSR when an exception is taken so that the CPSR can be restored after handling the exception. 2 Each exception handling mode can access its own SPSR. User mode and System mode do not have an SPSR because they are not exception handling modes. 3 The execution state bits, including the endianness state and current instruction set state can be accessed from the SPSR in any exception mode, using the MSR and MRS instruction. 4 You cannot access the SPSR using MSR or MRS in User or System mode.IMPLETION OF CPSR AND SPSR REGISTER IN ARMa.1 The ARM architecture provides a total of 37 registers, all of which are 32-bits long. However, these are arranged into several banks, with the accessible bank being governed by the current processor mode:a.2 A particular set of 13 General Purpose Registers (r0 - r12).a.3 A particular r13 - which is typically used as a stack pointer. This will be a different r13 for each mode, so allowing each exception type to have its own stack.a.4 A particular r14 - which is used as a link (or return address) register. Again, this will be a different r14 for each mode,r15 - whose only use is as the Program counter.a.5 The CPSR (Current Program Status Register) - this stores additional information about the state of the processor:a.6 And finally, in privileged modes, a particular SPSR (Saved Program Status Register). a.7 This stores a copy of the previous CPSR value when an exception occurs. This combined with the link register allows exceptions to return without corrupting processor state.Q 13) Write a modes of operation.A 13) Modes of operationDirect use of a block cipher is inadvisable. Enemy can build up “code book” of plaintext/ciphertext equivalents. Beyond that, direct use only works on messages that are a multiple of the cipher block size in length five standard Modes of Operation: a.1 Electronic Code Book(ECB), a.2 Cipher Block Chaining (CBC)a.3 Cipher Feedback (CFB)a.4 Output Feedback (OFB)a.5 Counter (CTR).ECB: a.1 Direct use of the block ciphera.2 Used primarily to transmit encrypted keysa.3 Very weak if used for general-purpose encryption; never use it for a file or a message.a.4 Attacker can build up codebook; no semantic securitya.5 We write {P}k → C to denote “encryption of plaintext P with key k to produce ciphertext C”.CBC: 
Fig Cipher Block Chain(CBC) CFB: Underlying block cipher used only in encryption mode 1 Feedback path actually incorporates a shift register: shift old cipher input left by n bits.2 Insert first n bits of previous ciphertext output8-bit CFB is good for asynchronous terminal traffic — but requires one encryption for each byte of plaintext, Errors propagate while bad data is in the shift register.3 17 bytes forCFB8 when using AES. Copes gracefully with deletion of n-bit unit.OFB: Properties of OFB 1 CTR2 PROPERTIES OF CTR2.a Another form of stream cipher2.b Frequently split the counter into two sections: message number and3 block number within the message3.a Active attacker can make controlled changes to plaintext3.b Highly parallelizable; no linkage between stages3.c Vital that counter never repeat for any given key. Q 15. Difference between PIC and ARM.A 15) PIC:PIC microcontroller refers to peripheral interface controller. Pic microcontrollers are available in 8 bit ,16 bit and 32bit. It supports PIC, UART, USART, CAN, LIAN , ethernet, SPI ,12S,commucation protocol. It has an effective instruction rate of 4 clock cycle per instruction. It uses a SRAM, flash memory. It is based on some features of RISC. It is based on hardware memory architecture. It has a very good community support. Its manufacturer is microchip. It is available with an average cost as compared to the features. Popular microcontroller includes PIC18IXX8,PIC32MXX ARM:ARM microcontroller refers to advanced RISC machine. ARM microcontroller is available in 32bit mostly also available in 64bit. It supports UART, USART,SPI,CAN,LAIN, 12C,DSP,SAI commutation protocol. It has an effective instruction rate of 1 clock cycle per instruction. It uses Flash, SDRAM, EEPROM memory. It is based on RISC instruction set architecture. It is based on modified Harvard architecture . ARM microcontroller family includes ARM v4, 5,6,7 and series. It has vast community support. Its manufacturers are apple , Nvidia ,Qualcomm, Samsung electronics and TI etc. Its available with a low cost as compare to the features. Popular microcontrollers include LPC2148, ARM Cortes-MO to ARM cortex M7 etc.
Fig.ARM7 Q 4) Write a short on ARM 9.A 4)Fig.ARM9 Q 5) Write a short note on ARM 11. A 5)- ARM Trust Zone® technology for on-chip security foundation (ARM1176JZ-S and ARM1176JZF-S processors)
- Thumb-2 technology (ARM1156(F)-S only) for enhanced performance, energy efficiency and code density
- Low power consumption:
- 0.21 mW/MHz (65G) including cache controllers
- Energy saving power-down modes address static leakage currents in advanced processes
- High performance integer processor
- 8-stage integer pipeline delivers high clock frequency (9 stages for ARM1156T2(F)-S)
- Separate load-store and arithmetic pipelines
- Branch Prediction and Return Stack
- High performance memory system design
- Supports 4-64k cache sizes
- Optional tightly coupled memories with DMA for multi-media applications
- High-performance 64-bit memory system speeds data access for media processing and networking applications
- ARMv6 memory system architecture accelerates OS context-switch
- Vectored interrupt interface and low-interrupt-latency mode speeds interrupt response and real-time performance
- Optional Vector Floating Point coprocessor for automotive/industrial controls and 3D graphics acceleration (ARM1136JF-S, ARM1176JZF-S and ARM1156T2F-S processors)
- All ARM11 family processors are delivered as ARM-Synopsys Reference Methodology compliant deliverables which significantly reduce the time to generate a specific technology implementation of the core and to generate a complete set of industry standard views and models.
Fig. ARM7 data flow model Features.1 Von Neuman Architecture Hence data coming through bus is either instruction or data (same memory)..2 The Sign extend hardware converts signed 8-bit & 16-bit numbers to 32-bit values as they are read from memory & placed in a register (for signed values), fill zeros if unsigned..3 Source operands (Rn & Rm) are read from the register file using the internal buses A & B respectively & result Rd is written back..4 The PC value is in the address register which is fed in to the incremented, then the incremented value is copied back in to r15..5 It is also written in to address register to be used as the address for the next instruction fetch..6 ALU: (The Arithmetic & logic Unit) or MAC (multiply & accumulate Unit) takes the register values Rn & Rm from A & B buses & computers a result)..7 Data processing instructions write the result in Rd directly to the register file..8 Load & Store instruction use the ALU to generate on Address to be to be held in the address register & broadcast on the address bus. Q 12) Explain CPSR and SPSR register.A 12 ) CPSR AND SPSR REGISTER Fig Cipher Block Chain(CBC) - No error propagation
- Active attacker can make controlled changes to plaintext
- OFB is a form of stream cipher
- PIC microcontroller family include PIC16,PIC17,PIC18,PIC24,PIC32.
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