MICRO
Unit 4Input- output, exceptions and interrupts Q1) Explain 2 ways of input/output of addressing?A1) I/O AddressingThe 80386 allows input/output to be performed in either of two ways:1. By means of a separate I/O address space (using specific I/O instructions)2. By means of memory-mapped I/O (using general-purpose operand manipulation instructions). 4.1.1 I/O Address Space 1. The 80386 provides a separate I/O address space, distinct from physical memory that can be used to address the input/output ports that are used for external 16 devices. 2. The I/O address space consists of 2^(16) (64K) individually addressable 8-bit ports; any two consecutive 8-bit ports can be treated as a 16-bit port; and four consecutive 8-bit ports can be treated as a 32-bit port. Thus, the I/O address space can accommodate up to 64K 8-bit ports, up to 32K 16-bit ports, or up to 16K 32-bit ports.3. The program can specify the address of the port in two ways. Using an immediate byte constant, the program can specify: 3.1 256 8-bit ports numbered 0 through 255.3.2 128 16-bit ports numbered 0, 2, 4, . . . , 252, 254.3.3 64 32-bit ports numbered 0, 4, 8, . . . , 248, 252. 4. Using a value in DX, the program can specify:4.1 8-bit ports numbered 0 through 655354.2 16-bit ports numbered 0, 2, 4, . . . , 65532, 655344.2 32-bit ports numbered 0, 4, 8, . . . , 65528, 65532 5. The 80386 can transfer 32, 16, or 8 bits at a time to a device located in the I/O space. Like double words in memory, 32-bit ports should be aligned at addresses evenly divisible by four so that the 32 bits can be transferred in a single bus access. 6. Like words in memory, 16-bit ports should be aligned at even-numbered addresses so that the 16 bits can be transferred in a single bus access. An 8-bit port may be located at either an even or odd address.7. The instructions IN and OUT move data between a register and a port in the I/O address space. The instructions INS and OUTS move strings of data between the memory address space and ports in the I/O address space. 4.1.2 Memory-Mapped I/O 1. I/O devices also may be placed in the 80386 memory address space. As long as the devices respond like memory components, they are indistinguishable to the processor.2. Memory-mapped I/O provides additional programming flexibility. Any instruction that references memory may be used to access an I/O port located in the memory space2. For example, the MOV instruction can transfer data between any register and a port; and the AND, OR, and TEST instructions may be used to manipulate bits Memory-mapped I/O performed via the full instruction set maintains the full complement of addressing modes for selecting the desired I/O device (e.g., direct address, indirect address, base register, index register, scaling). Q2) What are instruction I/O and explain two types of it in detail?A2) I/O Instructions 1. The I/O instructions of the 80386 provide access to the processor's I/O ports for the transfer of data to and from peripheral devices. These instructions have as one operand the address of a port in the I/O address space. There are two classes of I/O instruction:1.1 Those that transfer a single item (byte, word, or doubleword) located in a register.1.2. Those that transfer strings of items (strings of bytes, words, or doublewords) located in memory. These are known as "string I/O instructions" or "block I/O instructions". 1. Register I/O Instructions 1. The I/O instructions IN and OUT are provided to move data between I/O ports and the EAX (32-bit I/O), the AX (16-bit I/O), or AL (8-bit I/O) general registers. IN and OUT instructions address I/O ports either directly, with the address of one of up to 256 port addresses coded in the instruction, or indirectly via the DX register to one of up to 64K port addresses.2. IN (Input from Port) transfers a byte, word, or double word from an input port to AL, AX, or EAX. If a program specifies AL with the IN instruction, the processor transfers 8 bits from the selected port to AL. If a program specifies AX with the IN instruction, the processor transfers 16 bits from the port to AX. If a program specifies EAX with the IN instruction, the processor transfers 32 bits from the port to EAX.3.OUT(Output to Port) transfers a byte, word, or double word to an output port from AL, AX, or EAX. The program can specify the number of the port using the same methods as the IN instruction. 2. Block I/O Instructions 1. The block (or string) I/O instructions INS and OUTS move blocks of data between I/O ports and memory space. Block I/O instructions use the DX register to specify the address of a port in the I/O address space. INS and OUTSuse DX to specify:1.1 8-bit ports numbered 0 through 655351.2 16-bit ports numbered 0, 2, 4, . . . , 65532, 655341.3 32-bit ports numbered 0, 4, 8, . . . , 65528, 655322. Block I/O instructions use either SI or DI to designate the source or destination memory address. For each transfer, SI or DI are automatically either incremented or decremented as specified by the direction bit in the flags register.3. INS and OUTS, when used with repeat prefixes, cause block input or output operations. REP, the repeat prefix, modifies INS and OUTS to provide a means of transferring blocks of data between an I/O port and memory. These block I/O instructions are string primitives .4. They simplify programming and increase the speed of data transfer by eliminating the need to use a separate LOOP instruction or an intermediate register to hold the data.5. The string I/O primitives can operate on byte strings, word strings, or doubleword strings. After each transfer, the memory address in ESI or EDI is updated by 1 for byte operands, by 2 for word operands, or by 4 for doubleword operands. Q3) Explain what is Protection and I/O and two methods of it in detail?A3) 1. Two mechanisms provide protection for I/O functions:1.1 The IOPL field in the EFLAGS register defines the right to use I/O-related instructions.1.2 The I/O permission bit map of a 80386 TSS segment defines the right to use ports in the I/O address space.2. These mechanisms operate only in protected mode, including virtual 8086 mode; they do not operate in real mode. In real mode, there is no protection of the I/O space; any procedure can execute I/O instructions, and any I/O port can be addressed by the I/O instructions. 1. I/O Privilege Level1. Instructions that deal with I/O need to be restricted but also need to be executed by procedures executing at privilege levels other than zero. For this reason, the processor uses two bits of the flags register to store the I/O privilege level (IOPL). The IOPL defines the privilege level needed to execute I/O-related instructions.The following instructions can be executed only if CPL <= IOPL: 1.1 IN -- Input1.2 INS -- Input String1.3 OUT -- Output1.4 OUTS -- Output String1.5 CLI -- Clear Interrupt-Enable Flag1.6 STI -- Set Interrupt-Enable2. These instructions are called "sensitive" instructions, because they are sensitive to IOPL.3. To use sensitive instructions, a procedure must execute at a privilege level at least as privileged as that specified by the IOPL (CPL <= IOPL). Any attempt by a less privileged procedure to use a sensitive instruction results in a general protection exception.4. Because each task has its own unique copy of the flags register, each task can have a different IOPL. 5. A task whose primary function is to perform I/O (a device driver) can benefit from having an IOPL of three, thereby permitting all procedures of the task to perform I/O. Other tasks typically have IOPL set to zero or one, reserving the right to perform I/O instructions for the most privileged procedures. 2. I/O Permission Bit Map 1. The I/O instructions that directly refer to addresses in the processor's I/O space are IN, INS, OUT, OUTS. The 80386 has the ability to selectively trap references to specific I/O addresses. 2. The structure that enables selective trapping is the I/O Permission Bit Map in the TSS segment . The I/O permission map is a bit vector. The size of the map and its location in the TSS segment are variable. 3. The processor locates the I/O permission map by means of the I/O map base field in the fixed portion of the TSS. The I/O map base field is 16 bits wide and contains the offset of the beginning of the I/O permission map. The upper limit of the I/O permission map is the same as the limit of the TSS segment.4. In protected mode, when it encounters an I/O instruction (IN, INS, OUT, or OUTS), the processor first checks whether CPL <= IOPL. If this condition is true, the I/O operation may proceed.5. If not true, the processor checks the I/O permission map. (In virtual 8086 mode, the processor consults the map without regard for IOPL . 6. Each bit in the map corresponds to an I/O port byte address; for example, the bit for port 41 is found at I/O map base + 5, bit offset 1. Q4) Write a short note on identifying interrupts?A4) Identifying Interrupts 1. The processor associates an identifying number with each different type of interrupt or exception.2. The NMI and the exceptions recognized by the processor are assigned predetermined identifiers in the range 0 through 31. Not all of these numbers are currently used by the 80386; unassigned identifiers in this range are reserved by Intel for possible future expansion.3. The identifiers of the maskable interrupts are determined by external interrupt controllers (such as Intel's 8259A Programmable Interrupt Controller) and communicated to the processor during the processor's interrupt-acknowledge sequence.4. The numbers assigned by an 8259A PIC can be specified by software. Any numbers in the range 32 through 255 can be used. Table shows the assignment of interrupt and exception identifiers. Q5) Explain the three ways of identifying interrupts or exception ?A5) Exceptions are classified as faults, traps, or aborts depending on the way they are reported and whether restart of the instruction that caused the exception is supported.5.1 FaultsFaults are exceptions that are reported "before" the instruction causingthe exception. Faults are either detected before the instruction begins to execute, or during execution of the instruction. If detected during the instruction, the fault is reported with the machine restored to a state that permits the instruction to be restarted.5.2 TrapsA trap is an exception that is reported at the instruction boundary immediately after the instruction in which the exception was detected.5.3 AbortsAn abort is an exception that permits neither precise location of the instruction causing the exception nor restart of the program that caused the exception. Aborts are used to report severe errors, such as hardware errors and inconsistent or illegal values in system tables.
Q6) Explain enabling and disabling interrupts with their following conditions?A6) 1. The processor services interrupts and exceptions only between the end of one instruction and the beginning of the next.2. When the repeat prefix is used to repeat a string instruction, interrupts and exceptions may occur between repetitions. Thus, operations on long strings do not delay interrupt response.3. Certain conditions and flag settings cause the processor to inhibit certain interrupts and exceptions at instruction boundaries. 1. NMI Masks Further NMIsWhile an NMI handler is executing, the processor ignores further interrupt signals at the NMI pin until the next IRET instruction is executed. 2. IF Masks INTR1. The IF (interrupt-enable flag) controls the acceptance of external interrupts signalled via the INTR pin. When IF=0, INTR interrupts are inhibited; when IF=1, INTR interrupts are enabled. 2. As with the other flag bits, the processor clears IF in response to a RESET signal. The instructions CLI and STI alter the setting of IF.3. CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) explicitly alter IF (bit 9 in the flag register). These instructions may be executed only if CPL <= IOPL. A protection exception occurs if they are executed when CPL > IOPL. 3. RF Masks Debug FaultsThe RF bit in EFLAGS controls the recognition of debug faults. This permits debug faults to be raised for a given instruction at most once, no matter how many times the instruction is restarted. 4. MOV or POP to SS Masks Some Interrupts and Exceptions1. Software that needs to change stack segments often uses a pair of instructions; for example:MOV SS, AXMOV ESP, StackTop2. If an interrupt or exception is processed after SS has been changed but before ESP has received the corresponding change, the two parts of the stack pointer SS:ESP are inconsistent for the duration of the interrupt handler or exception handler.3. To prevent this situation, the 80386, after both a MOV to SS and a POP to SS instruction, inhibits NMI, INTR, debug exceptions, and single-step traps at the instruction boundary following the instruction that changes SS. Q7) Write a short note on Priority among Simultaneous Interrupts and Exceptions?A7) 1. If more than one interrupt or exception is pending at an instruction boundary, the processor services one of them at a time.2. The processor first services a pending interrupt or exception from the class that has the highest priority, transferring control to the first instruction of the interrupt handler. 3. Lower priority exceptions are discarded; lower priority interrupts are held pending. Discarded exceptions will be rediscovered when the interrupt handler returns control to the point of interruption. Q8) State and explain Interrupt Descriptor Table ?A8)1. The interrupt descriptor table (IDT) associates each interrupt or exception identifier with a descriptor for the instructions that service the associated event. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors. 2. Unlike the GDT and LDTs, the first entry of the IDT may contain a descriptor. To form an index into the IDT, the processor multiplies the interrupt or exception identifier by eight. 3. Because there are only 256 identifiers, the IDT need not contain more than 256 descriptors. It can contain fewer than 256 entries; entries are required only for interrupt identifiers that are actually used.4. The IDT may reside anywhere in physical memory. As the processor locates the IDT by means of the IDT register (IDTR). The instructions LIDT and SIDT operate on the IDTR. Both instructions have one explicit operand: the address in memory of a 6-byte area. 5. LIDT (Load IDT register) loads the IDT register with the linear base address and limit values contained in the memory operand.6. This instruction can be executed only when the CPL is zero. It is normally used by the initialization logic of an operating system when creating an IDT. An operating system may also use it to change from one IDT to another.7. SIDT (Store IDT register) copies the base and limit value stored in IDTR to a memory location. This instruction can be executed at any privilege level.8. Table Priority among Simultaneous Interrupts and Exceptions
Q9) State and explain three types of IDT Descriptors ?A9) 1. The IDT may contain any of three kinds of descriptor:1.1 Task gates1. A task gate descriptor provides an indirect, protected reference to a TSS.The SELECTOR field of a task gate must refer to a TSS descriptor. The value of the RPL in this selector is not used by the processor.2. The DPL field of a task gate controls the right to use the descriptor to cause a task switch. A procedure may not select a task gate descriptor unless the maximum of the selector's RPL and the CPL of the procedure is numerically less than or equal to the DPL of the descriptor. This constraint prevents untrusted procedures from causing a task switch.1.2 Interrupt gates1. An interrupt gate or trap gate points indirectly to a procedure which will execute in the context of the currently executing task .2. The selector of the gate points to an executable-segment descriptor in either the GDT or the current LDT. The offset field of the gate points to the beginning of the interrupt or exception handling procedure. 1.3 Trap gates1.An trap gate points indirectly to a procedure which will execute in the context of the currently executing task The selector of the gate points to an executable-segment descriptor in either the GDT or the current LDT. 2. The offset field of the gate points to the beginning of the interrupt or exception handling procedure. Q10) state and explain types of interrupt procedures?A10)An interrupt gate or trap gate points indirectly to a procedure which will execute in the context of the currently executing task The selector of the gate points to an executable-segment descriptor in either the GDT or the current LDT. The offset field of the gate points to the beginning of the interrupt or exception handling procedure.1. Stack of Interrupt Procedure1. Just as with a control transfer due to a CALL instruction, a control transfer to an interrupt or exception handling procedure uses the stack to store the information needed for returning to the original procedure. 2. An interrupt pushes the EFLAGS register onto the stack before the pointer to the interrupted instruction. 2. Returning from an Interrupt Procedure1. An interrupt procedure also differs from a normal procedure in the method of leaving the procedure. 2. The IRET instruction is used to exit from an interrupt procedure. IRET is similar to RET except that IRET increments ESP by an extra four bytes (because of the flags on the stack) and moves the saved flags into the EFLAGS register. 3. Flags Usage by Interrupt Procedure1. Interrupts that vector through either interrupt gates or trap gates cause TF (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS. By this action the processor prevents debugging activity that uses single-stepping from affecting interrupt response. A subsequent IRET instruction restores TF to the value in the EFLAGS image on the stack.2. The difference between an interrupt gate and a trap gate is in the effect on IF (the interrupt-enable flag). 4. Protection in Interrupt Procedures1. The privilege rule that governs interrupt procedures is similar to that for procedure calls: the CPU does not permit an interrupt to transfer control to a procedure in a segment of lesser privilege (numerically greater privilege level) than the current privilege level.2. An attempt to violate this rule results in a general protection exception. Because occurrence of interrupts is not generally predictable, this privilege rule effectively imposes restrictions on the privilege levels at which interrupt and exception handling procedures can execute. 3. Either of the following strategies can be employed to ensure that the privilege rule is never violated.4. Place the handler in a conforming segment. This strategy suits the handlers for certain exceptions (divide error, for example Q11) State and explain what interrupt task in detail is?A11)Interrupt Tasks1. A task gate in the IDT points indirectly to a task, The selector of the gate points to a TSS descriptor in the GDT.2. When an interrupt or exception vectors to a task gate in the IDT, a task switch results. Handling an interrupt with a separate task offers two advantages:3. The entire context is saved automatically.The interrupt handler can be isolated from other tasks by giving it a separate address space, either via its LDT or via its page directory.4. The actions that the processor takes to perform a task switch . The interrupt task returns to the interrupted task by executing an IRET instruction.If the task switch is caused by an exception that has an error code, the processor automatically pushes the error code onto the stack that corresponds to the privilege level of the first instruction to be executed in the interrupt task.5. When interrupt tasks are used in an operating system for the 80386, there are actually two schedulers: the software scheduler (part of the operating system) and the hardware scheduler (part of the processor's interrupt mechanism).6. The design of the software scheduler should account for the fact that the hardware scheduler may dispatch an interrupt task whenever interrupts are enabled.
Interrupt and Exception ID Assignments
Identifier Description
0 Divide error 1 Debug exceptions 2 Nonmaskable interrupt 3 Breakpoint (one-byte INT 3 instruction) 4 Overflow (INTO instruction) 5 Bounds check (BOUND instruction) 6 Invalid opcode 7 Coprocessor not available 8 Double fault 9 (reserved) 10 Invalid TSS 11 Segment not present 12 Stack exception 13 General protection 14 Page fault 15 (reserved) 16 Coprocessor error 17-31 (reserved) 32-255 Available for external interrupts via INTR pin |
Priority Class of Interrupt or Exception
HIGHEST Faults except debug faults Trap instructions INTO, INT n, INT 3 Debug traps for this instruction Debug faults for next instruction NMI interrupt LOWEST INTR interrupt |
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