undefined | unit 4 distributed memory architecture

ACA

UNIT 4

Distributed Memory Architecture

Q1) What Are the Major Difficulties Of Pipeline Conflicts In Processors Supporting Pipe Lining?

A1)

The following are the main reasons for pipe line conflicts in the processor:

When the same resource is accessed at the same time by two different segments it results in resource conflicts. The only way to resolve this problem is to use separate data memories.

In case an instruction's execution depends on the result of a previous instruction and that result is unavailable it leads to data dependency conflicts.

Instructions that change the count of the PC can cause a lot of problems. This is prevalent particularly in the case of Branch instructions. A method to resolve this issue is known as delayed load where certain instruction are made to execute in a delayed manner to avoid conflicts.

Q2) Explain Mesi?

A2)

The MESI protocol is also known as Illinois protocol due to its development at the University of Illinois at Urbana-Champaign and MESI is a widely used cache coherency and memory coherence protocol.

MESI is the most common protocol which supports write-back cache. Its use in personal computers became widespread with the introduction of Intel's Pentium processor to "support the more efficient write-back cache in addition to the write-through cache previously used by the Intel 486 processor"

Q3) Point Out The Characteristics Of The Risc Architecture?

A3)

RISC meaning reduced instruction set as the acronym say aims to reduce the execution times of instructions by simplifying the instructions.

The major characteristics of RISC are as follows:

Compared to normal instructions they have a lower number of instructions.

The addressing modes in case of RISC is also lower.

All the operations that are required to be performed take place within the CPU.

All instruction are executed in a single cycle hence have a faster execution time.

in this architecture the processors have a large number of registers and a much more efficient instruction pipeline.

Also the instruction formats are of fixed length and can be easily decoded.

Q4) Explain A Snooping Cache?

A4)

Snooping is the process where the individual caches monitor address lines for accesses to memory locations that they have cached. When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location.

Snarfing is where a cache controller watches both address and data in an attempt to update its own copy of a memory location when a second master modifies a location in main memory

Q5) What Are The Steps Involved In An Instruction Cycle?

A5)

Any program residing in the memory contains a set of instruction that need to be executed by the computer in a sequential manner. This cycle for every instruction is known as the instruction cycle . The cycle consists of the following steps:

Fetch instruction: Like the name stated in this process the cpu fetches the instruction from the memory. The PC get loaded with the address of the instruction.

Decode: the instruction: In this process the instruction gets decoded by the processor.In case the instruction has an indirect address the effective address is read from the memory.Fetch the operand from the memory

Execution: once the instruction gets decoded the processor executes the instruction.

Result: Store the result in the appropriate place.

Q6) Explain What Are Five Stages In A Dlx Pipeline?

A6)

The instruction sets can be differentiated by:

Operand storage in the CPU

Number of explicit operands per instruction

Operand location

Operations

Type and size of operands

Q7) Explain The Components Of The Ven Neumann Architecture?

A7)

The main components of the Von Neumann architecture were as follows:

It consisted of a main memory which would be used to store all the data and instructions.

It would consist of an arithmetic logical unit also known as the ALU. This part was to be able to work with binary data.

It also comprised of a control unit which would be responsible for the interpretation of instructions and their execution.

The control unit would also be controlled by the control unit itself.

Q8) What Is External Interrupts?

A8)

These types of interrupts generally come from external input / output devices which are connected externally to the processor. They are generally independent and oblivious of any programming that is currently running on the processor.

Q9) Explain Briefly Six Different Types Of Addressing Modes Of An Instruction?

A9)

The different types of instructions are as follows:

Immediate Mode: As the name suggests the instruction in itself contains the operand.

Register Mode: In this mode the operands of an instruction are placed in the registers which themselves are placed inside the CPU.

Direct address mode: The address part of an instruction in this mode is the effective address.

Indexed addressing mode: In this mode in order to obtain the effective address the contents of the index register is added to the instructions address part.

Relative address mode: In this mode in order to find out the effective address the contents of the program counter are added to the address part of the instruction.

Q10) What Is Internal Interrupts?

A10)

They are also known as traps and their causes could be due to some illegal operation or the erroneous use of data. Instead of being triggered by an external event they are usually triggered due to any exception that has been caused by the program itself. Some of the causes of these types of interrupts can be due to attempting a division by zero or an invalid opcode etc.

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