undefined | unit 1 basic real time concepts and hardware consideration

RTOS

Unit – 1

Basic Real Time Concepts & Hardware Consideration

Q(1) Explain the Basic Terminology in Basic Real Time Concepts.

A 1)

Basic Terminology:

System:
A system is a mapping of a set of inputs into a set of outputs.

Response Time:
The time between the presentation of a set of inputs to a system and the
realization of the required behaviour, including the availability of all associated outputs, is called the response time of the system.

Real - Time System ( I ):
A real - time system is a computer system that must satisfy bounded response -time constraints or risk severe consequences, including failure.

Real - Time System ( II ):
A real - time system is one whose logical correctness is based on both the
correctness of the outputs and their timeliness.

Failed System:
A failed system is a system that cannot satisfy one or more of the requirements stipulated in the system requirements specification.

Embedded System:
An embedded system is a system containing one or more computers (or
processors) having a central role in the functionality of the system, but the
system is not explicitly called a computer.

Soft Real - Time System:
A soft real - time system is one in which performance is degraded but not
destroyed by failure to meet response - time constraints.

Hard Real - Time System:
A hard real - time system is one in which failure to meet even a single deadline may lead to complete or catastrophic system failure.

Firm Real - Time System:
A firm real - time system is one in which a few missed deadlines will not lead
to total failure, but missing more than a few may lead to complete or catastrophic system failure.

Q(2) Explain A Sampling of Hard, Firm, and Soft Real - Time Systems.

A 2)

A Sampling of Hard, Firm, and Soft Real - Time Systems:

System	Real Time Classification	Explanation
Avionics weapons delivery system in which pressing a button launches an air - to - air missile	Hard	Missing the deadline to launch the missile within a specified time after pressing the button may cause the target to be missed, which will result in catastrophe
Navigation controller for an autonomous weed - killer robot	Firm	Missing a few navigation deadlines causes the robot to veer out from a planned path and damage some crops
Console hockey game	Soft	Missing even several deadlines will only degrade performance

Q(3) Explain Real Time Design Issues.

A 3)

Fig.1: A variety of disciplines that affect real - time systems engineering

The design and implementation of real - time systems requires attention to
numerous practical issues. These include:

The selection of hardware and system software, and evaluation of the
trade - off needed for a competitive solution, including dealing with
distributed computing systems and the issues of concurrency and
synchronization.

Specification and design of real - time systems, as well as correct and inclusive representation of temporal behaviour.

Understanding the nuances of the high - level programming language(s)
and the real - time implications resulting from their optimized compilation
into machine - language code.

Optimizing (with application - specific objectives) of system fault tolerance
and reliability through careful design and analysis.

The design and administration of adequate tests at different levels of
hierarchy, and the selection of appropriate development tools and test
equipment.

Taking advantage of open systems technology and interoperability.

An open system is an extensible collection of independently written applications that cooperate to function as an integrated system.

For example, several versions of the open operating system, Linux, have emerged for use in various real - time applications (Abbott, 2006 ). Interoperability can be measured in terms of compliance with open system standards, such as the real - time CORBA ( common object request broker architecture ) standard (Fay - Wolfe et al., 2000 ).

Finally, estimating and measuring response times and (if needed) reducing them. Performing a schedulability analysis, that is, determining and guaranteeing deadline satisfaction, a priori.

Q(4) Explain Practical Examples and Applications of Real-Time Systems

A 4)

Practical Examples and Applications of Real-Time Systems:

Domain	Applications
Aerospace	Flight Control Navigation Pilot Interface
Civilian	Automotive Systems Elevator Control Traffic Light Control
Industrial	Automated Inspection Robotic Assembly Line Welding Control
Medical	Intensive Care Monitors Magnetic Resonance Imaging Remote Surgery
Multimedia	Console Games Home Theatres Simulators

Any application that monitors static or dynamic behaviour of system continuously with respect to time is real time system.

Traffic control systems or Process control-based applications in industries are its appropriate examples.

Q(5) Explain Brief History of Real Time Systems

A 5)

Brief History of Real Time Systems:

Year	Landmark	Developer	Development	Innovations
1947	Whirlwind	IBM	Flight Simulator	Ferrite Core Memory(“Fast”)High Level Language
1957	SAGE	IBM	Air Defense	Designed for Real Time
1958	Scientific 1103A	Univac	General Purpose	Asynchronous Interrupt
1959	SABRE	IBM	Airline Reservation	Hub-Go-Ahead Policy
1962	Basic Executive	IBM	General Purpose	Diverse Real Time Scheduling
1963	Basic Executive-II	IBM	General Purpose	Disk -resident system/User Programs
1970s	RSX, RTE	DEC, HP	Real-time operating systems	Hosted By Mini-Computers
1973	Rate-Monotonic System	Liu & Leyland	Fundamental Theory	Upper bound on utilisation for schedulable systems
1970s & 1980s	RMX-80, MROS 68K,VRTS,etc.	Various	Real-Time operating systems	Hosted by microprocessors
1983	Ada 83	U.S. DoD	Programming Language	For mission-critical embedded systems
1995	Ada 95	Community	Programming Language	Improved version of Ada 83
2000s	-	-	Various Advances in hardware,open-source,and commercial system software & tools	A continuously growing range of innovative applications that can be Real-Time

Q(6) Explain Basic Architecture in details.

A 6)

Basic Architecture:

Fig.2: Internal structure of a simplified CPU. The Instruction Access and Data
The CPU is the core unit where instruction processing takes place; it consists of a control unit, an internal bus, and a data path, as illustrated in Above Figure.

The data path contains a multi - function arithmetic - logic unit
(ALU), and a bank of work registers, as well as a status register.

The control unit interfaces to the system bus through a program counter register (PCR) that addresses the external memory location from which the next instruction is going to be fetched to an instruction register ( IR ).

Von-Newman Architecture:

The traditional von Neumann computer architecture, also known as the
Princeton architecture, is used in numerous commercial processors and can be depicted with only three elements: a central processing unit ( CPU), a system bus, and memory.

Fig.3. Von Neumann architecture with slightly enhanced system bus for programmed input/output.

Instruction Processing:

Instruction processing consists of multiple consecutive phases taking a varying number of clock cycles to complete. These independent phases form jointly an instruction cycle.

Every instruction is represented by its unique binary code that is stored in the memory, and a stream of such codes forms a machine - language program

Fig.4.Phases of Instruction Processing vs. Clock Cycles

Q(7) Explain Peripheral Interfacing (I/O) in detail.

Ans-

Peripheral Interfacing (I/O):

The fundamental practices for input and output handling are still the same as in the late seventies:
• Polled I/O
• Interrupt - driven I/O
• Direct memory access

Polled I/O:

In a polled I/O system, the status of the I/O device is checked periodically, or, at least, regularly. Therefore, such I/O activity is software controlled; only accessible status and data registers are needed in the hardware side.

Interrupt - driven I/O:

Interrupt - driven I/O processing has remarkable advantages over the straightforward polled I/O: the service latency can, in general, be reduced and made less uncertain without increasing the loading of the CPU.

Fig.5: Interrupt - identification procedure between the CPU and PIU using vectored interrupt.

Analog and Digital Input/Output:

The core categories are outlined below:

Analog

Digital parallel

Digital pulse

Digital serial

Digital waveform

Q(8) Explain Memory in detail.

A 8)

Memory:

Volatile RAM versus non-volatile ROM is the traditional distinction between the two principal groups of semiconductor memory, where RAM states for random - access memory and ROM for read - only memory.

Electrically erasable programmable ROM (EEPROM) and its close relative Flash are based on the dynamic floating - gate principle and they both can be rewritten in a similar way as RAM devices.

However, the erasing and writing process of those ROM - type devices is much slower than in the case of RAM.

There are two classes of RAM devices: static RAM (SRAM) and dynamic RAM (DRAM).

Either or both of these classes are used also in real – time systems. A single SRAM - type memory cell needs typically six transistors to implement a bistate flip - flop structure, while a DRAM cell can be implemented with a single transistor and capacitor only.

Below is a sampled evolution path of DRAM modules with advanced access modes in their order of appearance (from the late eighties to 2007):
• Fast page mode ( FPM ) DRAM
• Extended data output ( EDO ) DRAM
• Synchronous DRAM ( SDRAM )
• Direct Rambus DRAM ( DRDRAM

Double data rate 3 synchronous DRAM ( DDR3 SDRAM )

Fig.6: Hierarchical memory organization with two cache levels, L1 and L2, between the CPU and main memory.

Fig.7: Interface lines of a generic memory component

Q(9) Explain Memory in detail.

A 9)

Memory:

Electrically erasable programmable ROM (EEPROM) and its close relative Flash are based on the dynamic floating - gate principle and they both can be rewritten in a similar way as RAM devices.

However, the erasing and writing process of those ROM - type devices is much slower than in the case of RAM.

There are two classes of RAM devices: static RAM (SRAM) and dynamic RAM (DRAM).

Fig.6: Hierarchical memory organization with two cache levels, L1 and L2, between the CPU and main memory.

Fig.7: Interface lines of a generic memory component

Q(10) Explain Cache and Direct Memory Access in detail.

A 10)

Cache:

The basic operation of the cache is as follows. Suppose the CPU requests the content of a DRAM location.

First, the cache controller checks the address tags to see if the particular location is in the cache. If present, the data is immediately retrieved from the cache, which is significantly faster than a fetch from main memory.

However, if the needed data is not in the cache, the cache contents must be written back and the required new block loaded from main memory to the cache.

The needed data is then delivered from the cache to the CPU, and the address tags are updated correspondingly by the cache controller.

Direct Memory Access:

In DMA, access to the computer’s memory is given to other devices
in the system without any CPU intervention.

That is, data is transferred directly between main memory and some external device.

Here, a separate DMA controller is required unless the DMA - handling circuitry is integrated into the CPU itself.

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