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FHDL

UNIT-1Introduction Q1) Write a short note on HDL?A1)Hardware description language (HDL) is a specially designed computer language used to program electronic and digital logic circuits. The structure, operation and design of the circuits are programmable using HDL. HDL includes a textual description consisting of operators, expressions, statements, inputs and outputs. Instead of generating a computer executable file, the HDL compilers provide a gate map. The gate map obtained is then downloaded to the programming device to verify the operations of the desired circuit. The language helps to characterize any digital circuit in the form of structural, behavioral and gate level and it is found to be an excellent programming language for FPGAs and CPLDs.The three common HDLs are Verilog, VHDL, and SystemC. Of these, SystemC is the latest. The HDLs will grant fast design and better verification. In most of the industries, Verilog and VHDL are used. Verilog, one of the main Hardware Description Language standardized as IEEE 1364 is used for designing all types of circuits. It consists of modules and the language allows Behavioral, Dataflow and Structural Description. VHDL (Very High Speed Integrated Circuit Hardware Description Language) is standardized by IEEE1164. The design is formed of entities consisting of multiple architectures. SystemC is a language that consist a set of C++classes and macros. It allows electronic system level and transaction modeling.Need for HDLsThe Moore’s Law in the year 1970 has brought a strong change in the field of IC technology. This change has made the developers to bring out complex digital and electronic circuits. But the problem was the non-availability of a better programming language allowing hardware and software code sign. Complex digital circuit designs require more time for development, synthesis, simulation and debugging. The arrival of HDLs has helped to solve this problem by allowing each module to be worked by a separate team.All the goals like power, throughput, latency (delay), test coverage, functionality and area consumption required for a design can be known by using HDL. As a result, the designer can make the essential engineering tradeoffs and can develop the design in a better and powerful way. Simple syntax, expressions, statements, concurrent and sequential programming is also necessary while describing the electronics circuits. All these features can be obtained by using a hardware description language. Now while comparing HDL and C languages, the main distinction is that HDL gives the timing information of a design. Q2) Explain the Structure of the VHDL ModuleA2)The VHDL module has two major constructs: entity and architecture. Entity declares the input and output signals of the system to be described and is given a name or identifier by the user. VHDL is case insensitive; for example, the two entity names Half_ADDER and half_adder are treated as the same name. The name should start with an alphabetical letter and can include the special character underscore (_). Declarations include the name and type of the inputs and outputs of the system. The inputs and outputs here are called input ports and output ports. The name of the port is user selected, and it has the same requirements as the entity’s name. entity Half_adder isport(a: in bit; b : in bit; S : out bit;C: out bit);end half_adder;The word entity is a predefined word. The name of the entity is Half_adder. This name is user selected and does not convey any information about the system; it is just an identifier. The entity could have been given any other name. VHDL does not know that the entity Half_adder describes a half adder simply by its name. The entity here has two input ports and two output ports. The term is is a predefined word and must be written after the name of the entity. The word port is predefined. The names of the input ports are a and b, and they must be followed by a colon (:). The predefined word in instantiates the mode of the port as an inputThe type of these input signals is bit and determines the allowed values that signals a and b can take. Type bit allows the signal to take only either logic 0 or logic 1. There are several other types, such as std_logic, real, and integer. The entity also has two output ports, S and C; they are declared as outputs with the predefined word out, and their type is bit. The order in which the input and output ports are written inside the parentheses is irrelevant. The output ports could have been listed before the input ports.The last line of the entity’s code uses the predefined word end, which ends the entity. The name of the entity can follow the word end, as in end Half_adder, or the name of the entity can be omitted and only end is entered.The semicolon (;) is an important character in HDL. It is used as a separator similar to the carriage return character used in C language. Ports can be declared in, out, inout, buffer, or linkageThe second construct of the VHDL module, the architecture, describes the relationship between the inputs and outputs of the system. Architecture has to be bound to an entity. This relationship can be described using several sources; one of these sources is the Boolean function of the outputs. Multiple architectures can be bound to the same entity, but each architecture can be bound to only one entity. The architecture is declared by the predefined word architecture, followed by a user-selected name; this name follows the same name-selecting guidelines as the entity.The predefined word of binds the architecture to the entity. Binding here means the information listed in the entity is visible to the architecture.

Example of Entity Architecture

entity Half_adder is

port(x: in bit; y : in bit; S : out bit; C: out bit);

end half_adder;

architecture add_half of Half_adder is

begin

S <= x xor y; -- statement 1

C <= x and y; -- statement 2

--Blank lines are allowed

end add_half;

In the above example, the architecture add _half recognizes the information declared in the entity, such as the name and type of ports x, y, S, and C. After entering the name of the entity, the predefined word is must be entered. The architecture’s body starts with the predefined word begin, followed by statements that detail the relationship between the outputs and inputs.In above example, the body of the architecture includes two statements. The two hyphens (--) signal that a comment follows. Statements 1 and 2 constitute the body of the architecture; they are signal assignment statements. The two statements describe the relationship between the output ports S and C and the input ports x and y. The xor and and are called logical operators; they simulate EXCLUSIVE- OR and AND logic, respectively. The architecture is concluded by the predefined word end. The name of the architecture can follow, if desired, the predefined word end. Leaving blank line(s) is allowed in the module; also, spaces between two words or at the beginning of the line are allowed. Q3) Explain structure of the Verilog Module.A3)

Verilog module has declaration and body. In the declaration, the name, inputs, and outputs of the module are entered. The body shows the relationship between the inputs and the outputs.

Example of a Verilog Module

module Half_adder(x,y,S,C);

input x,y;

output S, C;

// Blank lines are allowed

assign S = x ^ y; // statement 1

assign C= x & y; // statement 2

endmodule

The name of the module is a user-selected Half_adder. In contrast to VHDL, Verilog is case sensitive. Half_adder, half_adder, and half_addEr are all different names. The name of the module should start with an alphabetical letter and can include the special character underscore (_). The declaration of the module starts with the predefined word module followed by the user-selected name. The names of the inputs and outputs (they are called input and output ports) follow the same guidelines as the module’s name.

They are written inside parentheses separated by a comma. The parenthesis is followed by a semicolon. In above example, x, y, S, and C are the names of the inputs and outputs. The order of writing the input and output ports inside the parentheses is irrelevant. We could have written the module statement as:

module half_adder (S, C, x, y);

The semicolon (;) plays the same rule as in VHDL module; it is a line separator. Carriage return here does not indicate a new statement, the semicolon does. Following the module statement, the input and output port modes are declared. For example, the statement input a; declares signal a as an input port.

In contrast to VHDL, the type of the input and output port signals need not be declared. The order of writing the inputs and outputs and their declaration is irrelevant. For example, the inputs and outputs can be written as:

module half_adder (x,y, S, C);

output S;

output C;

input x;

input y;

Also, more than one input or output could be entered on the same line by using a comma (,) to separate each input or output as:

module half_adder (x,y, S, C);

output S, C;

input x, y;

Statements 1 and 2 in above example are signal assignment statements. In statement 1, the symbol ^ represents an EXCULSIVE-OR operation; this symbol is called a logical operator. So, statement 1 describes the relationship between S, x, and y as S = x xor y. In statement 2, the symbol & represents an AND logic; the symbol is called a logical operator. So, statement 2 describes the relationship between C, x, and y as C = x and y. The double slash (//) is a comment command where a comment can be entered.

If the comment takes more than one line, a double slash or pair (/*……..*/) can be used. The module is concluded by the predefined word endmodule. Leaving blank lines is allowed in the module; also, spaces between two words or at the beginning of the line are allowed.

Q4) List and explain various types of descriptions.A4)Several styles of code writing can be used to describe the system

Data flow,

Behavioral,

Structural,

Switch level,

Mixed type, and

Mixed language.

Data flow description: Data flow describes how the system’s signals flow from the inputs to the outputs. Usually, the description is done by writing the Boolean function of the outputs. The data-flow statements are concurrent; their execution is controlled by events.

Example-

entity Half_adder is

port(x: in bit; y : in bit; S : out bit;

C: out bit);

end half_adder;

architecture add_half of Half_adder is

begin

S <= x xor y; -- statement 1

C <= x and y; -- statement 2

--Blank lines are allowed

end add_half;

Using Verilog

module Half_adder(a,b,S,C);

input a,b;

output S, C;

// Blank lines are allowed

assign S = a ^ b; // statement 1

assign C= a & b; // statement 2

endmodule

2. Behavioral Description

A behavioral description models the system as to how the outputs behave with the inputs; usually, a flowchart is used to show this behavior.

YES

In the half adder, the S output can be described as “1” if the inputs x and y are not equal, otherwise S = “0,”. The output C can be described as acquiring a value of “1” only if each input (x and y) is “1.” The HDL behavioral description is the one where the architecture or the module contains the predefined word process (VHDL) or always or initial. Behavioral description is usually used when the Boolean function or the digital logic of the system is hard to obtain.

Example of Behavioral Description

VHDL1B Description

entity Half_adder is

port(x: in bit; y : in bit; S : out bit;

C: out bit);

end half_adder;

architecture beh_half of Half_adder is

begin

process (x, y)

begin

if (x /= y) then

S <= ‘1’;

else

S <= ‘0’;

--Blank lines are allowed

end if;

end process;

end beh_half;

Verilog Description

module Half_adder(x,y,S,C);

input x,y;

output S, C;

reg S,C;

// Blank lines are allowed

always @ (x,y)

begin

if (x != y)

S = 1’y1;

else

S = 1’y0;

end

endmodule

3. Structural Description:

Structural description models the system as components or gates. This description is identified by the presence of the keyword component in the architecture (VHDL) or gates construct such as and, or, and not in the module (Verilog).

Example of Structural Description

VHDL Description

entity Half_adder is

port(a: in bit; b : in bit; S : out bit;

C: out bit);

end half_adder;

architecture struct_exple of Half_adder is

component xor2

--The above statement is a component statement

port(I1, I2 : in std_logic;

O1 : out std_logic);

end component;

component and2

port(I1, I2 : in std_logic;

O1 : out std_logic);

end component;

begin

X1: xor2 port map (a,b, S);

A1: and2 port map (a,b, C);

end struct_exple;

Verilog Description

module Half_adder1(a,b,S,C);

input a, b;

output S,C;

and a1(C,a,b);

//The above statement is AND gate

xor x1(S,a,b);

//The above statement is EXCLUSIVE-OR gate

Endmodule

4. Switch-Level Description:

The switch-level description is the lowest level of description. The system is described using switches or transistors. Some of the Verilog predefined words used in the switch level description are nmos, pmos, cmos, tranif0, tran, and tranif1. VHDL does not have built-in switch-level primitives, but a construct package can be built to include such primitives.

An Example of A Switch-Level Description

VHDL Description

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Inverter is

Port (y : out std_logic; a: in std_logic );

end Inverter;

architecture Invert_switch of Inverter is

component nmos

--nmos is one of the key words for switch-level.

port (O1: out std_logic; I1, I2 : in std_logic);

end component;

component pmos

--pmos is one of the key words for switch-level.

port (O1: out std_logic ;I1, I2 : in std_logic);

end component;

for all: pmos use entity work. mos (pmos_behavioral);

for all: nmos use entity work. mos (nmos_behavioral);

--The above two statements are referring to a package mos

constant vdd: std_logic := ‘1’;

constant gnd : std_logic:= ‘0’;

begin

p1 : pmos port map (y, vdd, a);

n1: nmos port map (y, gnd, a);

end Invert_switch;

Verilog Description

module invert(y,a);

input a;

output y;

supply1 vdd;

supply0 gnd;

pmos p1(y, vdd, a);

nmos n1(y, gnd, a);

/*The above two statement are using the two primitives

pmos and nmos*/

endmodule

5. Mixed type description:

Mixed-type or mixed-style descriptions are those that use more than one type or style of the above-mentioned descriptions. In fact, most of the descriptions of moderate to large systems are mixed. Some parts of the system may be described using one type and others using other types of description.

6. Mixed language description:

The mixed-language description is a newly added tool to HDL description. The user now can write a module in one language (VHDL or Verilog) and invoke or import a construct (entity or module) written in the other language.

Example of Mixed-Language Description

module Full_Adder1 ( x,y, cin, sum, carry);

input x,y,cin;

output sum, carry;

wire c0, c1, s0;

HA H1 (y, cin, s0,c0);

// Description of HA is written in VHDL in the

// entity HA

..................

endmodule

library IEEE;

use ieee.std_logic_1164.all;

entity HA is

--For correct binding between this VHDL code and the above

--Verilog code, the entity has to be named here as HA

port (a, b : in std_logic; s, c: out std_logic);

end HA;

architecture HA_Dtflw of HA is

begin

s <= a xor b;

c <= a and b;

end HA_Dtflw;

Q6) What are the various modes in which port can be used in VHDL?A6) A simple definition of ports can be stated as a communication means between the system to be described and the environment.In VHDL, ports can take one of the following modes:

in: The port is only an input port. In any assignment statement, the port should appear only on the right-hand side of the statement (i.e., the port is read).

out: The port is only an output port. In any assignment statement, the port should appear only on the left-hand side of the statement (i.e., the port is updated).

buffer: The port can be used as both an input and output but can have only one source (i.e., limited fan out). The port can appear on either the left- or right-hand side of an assignment statement. A buffer port can only be connected to another buffer port or to a signal that also has only one source.

inout: The port can be used as both an input and output.

linkage: Same as inout but the port can only correspond to a signal.

Q7) What are the various modes in which port can be used in Verilog?A7) Verilog ports can take one of the following three modes:

input: The port is only an input port. In any assignment statement, the port should appear only on the right-hand side of the statement (i.e., the port is read).

output: The port is an output port. In contrast to VHDL, the Verilog output port can appear in either side of the assignment statement.

inout: The port can be used as both an input and output. The inout port represents a bidirectional bus.

Q8) List various logical operators used in both verilog and VHDL.A8) These operators perform logical operations, such as AND, OR, NAND, NOR, NOT, and XOR. The operation can be on two operands or on a single operand. The operand can be single or multiple bits.

VHDL Logical Operator	Verilog Logical Operator	Equivalent logic	Operand type	Result type
AND	&	AND gate	Bit	Bit
OR	\|	OR gate	Bit	Bit
NAND	~(&)	NAND gate	Bit	Bit
NOR	~(\|)	NOR gate	Bit	Bit
XOR	^	XOR gate	Bit	Bit
XNOR	~^	XNOR gate	Bit	Bit
NOT	~	NOT gate	Bit	Bit

Q9) List various Relational and Arithmetic operators used in both Verilog and VHDL.A9)

Relational Operators:

Relational operators are implemented to compare the values of two objects. The result returned by these operators is in Boolean: false (0) or true (1).

Operators in VHDL	Operators in Verilog	Description	Result type in VHDL	Result type in Verilog
=	==	Equality	Boolean	0,1,x
/=	!=	Inequality	Boolean	0,1,x
<	<	Less than	Boolean	0,1,x
<=	<=	Less than or equal	Boolean	0,1,x
>	>	Greater than	Boolean	0,1,x
>=	>=	Greater than or equal	Boolean	0,1,x
	===	Equality inclusive		0,1
	!==	Inequality inclusive		0,1
	?	Conditional operator		0,1,x

Example

If (A = B) then .....

A is compared to B. If A is equal to B, the value of the expression (A = B) is true (1); otherwise, it is false (0).

if (A == B) .…….

If the value of A or B contains one or more “don’t care” or z bits, the value of the expression is unknown. Otherwise, if A is equal to B, the value of the expression is true (1). If A is not equal to B, the value of the expression

is false (0).

2. Arithmetic Operators:

Arithmetic operators can perform a wide variety of operations, such as addition, subtraction, multiplication, and division.

VHDL

Operator	Description	Input type	Result type
+	Addition	A numeric B numeric	Numeric
-	Subtraction	A numeric B numeric	Numeric
*	Multiplication	A integer or real B integer or real	Same as A
*	Multiplication	A physical B integer or real	Same as A
*	Multiplication	A integer or real B physical	Same as B
/	Division	A integer or real B integer or real	Same as A
/	Division	A physical B integer or real	Same as B
/	Division	A integer or real B physical	Same as A
mod	Modulus	A only integer B only integer	Integer
Rem	Remainder	A only integer B only integer	Integer
Abs	Absolute	A numeric	Positive numeric
&	Concatenation	A numeric or array B numeric or array	Same as A
**	Exponent	A real or integer B only integer	Same as A

Verilog

Operator	Description	Input type	Result type
+	Addition	A numeric B numeric	Numeric
-	Subtraction	A numeric B numeric	Numeric
*	Multiplication	A numeric B numeric	Numeric
/	Division	A numeric B numeric	Numeric
%	Modulus	A numeric, not real B numeric, not real	Numeric, not real
**	Exponent	A numeric B numeric	Numeric
{,}	Concatenation	A numeric or array B numeric or array	Same as A
{N{A}}	Repetition	A numeric or array	Same as A

Note:

The precedence of the arithmetic operators in VHDL or Verilog is the same as in C. The precedence of the major operators is listed below from highest to lowest:

* / mod (%)

+ -

Q10) List various Shift and Rotate operators used in both verilog and VHDL.A10) Shift and Rotate Operator: Shift and rotate operators are implemented in many applications, such as in multiplication and division. A shift left represents multiplication by two, and a shift right represents division by two.VHDL

Operation	Description Before Shift	Operand A After Shift	Operand A
A sll 1	Shift A one position left logical	1110	1100
A sll 2	Shift A two position left logical	1110	10xx
A srl 1	Shift A one position right logical	1110	x111
A srl 2	Shift A two position right logical	1110	xx11
A sla 1	Shift A one position left arithmetic	1110	110x
A sra 1	Shift A one position right arithmetic	1110	1111
A rol 1	Rotate A one position left	1110	1101
A ror 1	Rotate A one position right	1110	0111

Verilog

Operation	Description Before Shift	Operand A After Shift	Operand A
A<<1	Shift A one position left logical	1110	1100
A<<2	Shift A two position left logical	1110	1000
A>>1	Shift A one position right logical	1110	0111
A>>2	Shift A two position right logical	1110	0011
A.>>> 2	Shift A two positions right arithmetic	1110	1111
A.<<<2	Shift A two positions left arithmetic	1110	1000

Q11) Explain all data types used in VHDL.A11) Data types can be classified into five groups depending on the nature of the values the object can assume: scalar, composite, access, file, and other.

Scalar type:

The values that a scalar can assume are numeric. Numeric values can be integer, real, physical, Boolean, or characters when stored as ASCII.

The following types constitute the scalar types.

Bit Type

The only values allowed here are 0 or 1. It is used to describe a signal that takes only 1 (high) or 0 (low).

An example of implementing this type is when the type of a port signal is described as:

port (I1, I2 : in bit; O1, O2 : out bit);

Signals I1, I2, O1, and O2 can assume only 0 or 1.

b. Boolean Type

This type can assume two values: false (0) or true (1). Both true and false are predefined words. One of the most frequent applications

of the Boolean type is in the if statement

Example-

If (y = A) then

S := ‘1’;

else

S := ‘0’;

end if;

The output of the first line, If (y =A), is Boolean: it is either true or false. If true, then S = 1; if false, S = 0. Boolean can also be specified as

the port type:

port (I1, I2 : in bit; O1 : out bit; O2 : Boolean);

c. Integer Type

As the name indicates, this type covers all integer values; the values can be negative or positive. The range is from –2,147,483,648 to +2,147,483,647. The user can specify a shorter range by using the predefined word range.

The exponent has to be of type integer, such as x**2 or x**y, where y is declared as integer. The port can also be declared as type integer:

port (I1 : in natural; I2 : in bit; O1 : out integer; O2 : Boolean);

Another predefined type positive restricts the values an object can take to be positive and higher than 0.

d. Real Type

This type accepts fractions, such as .4502, 12.5, and –5.2E–10 where E–10 = 10–10.

An example of using real type is:

port (I1 : in natural; I2 : in real; O1 : out integer; O2 : Boolean);

e. Character Type

This type includes characters that can be used to print a message using, for example, the predefined command report, such as:

report (“Variable x is greater than Y”);

The report statement is very similar to the print statement in C language. Some format can be added to the characters printed

by report:

report (“Variable x is greater than Y.”) & CR &

(“Variable x is > 2.34.”);

where & is the concatenation operator, and CR is a predefined word for carriage return.

subtype and type, if used, assign numeric value to each character, as follows:

subtype wordChr is character;

type string_chr is array (N downto 0) of wordChr;

In addition, subtype, type, and array are predefined words. The two statements above declare an array of N + 1 elements, and each element is a character. The characters are associated with ASCII values. For example,

character A has the ASCII value of 41 in hex.

f. Physical Type

This type has values that can be measured in units, such as time (e.g., second, millisecond, microsecond) and voltage (e.g., volt, millivolt, microvolts). An example of type time is:

constant Delay_inv : time := 1 ns;

The above statement states that the constant Delay_inv is of type time, and its initial value is one nanosecond (1 ns). The word time is predefined.

g. User-Defined Types

The user can define a type by using the predefined word type as shown below:

type op is (add, mul, divide, none);

variable opcode : op := mul;

Type op is user defined. The variable opcode is of type op and can therefore be instantiated to: add, mul, divide, or none.

h. Severity Type

This type is used with the assert statement. An object with type severity can take one of four values: note, warning, error, or failure. An example of this type is as follows:

assert (Flag_full = false);

report “The stack is full”;

severity failure;

2. Composite Type:

The composite type is a collection of values. There are three composite types: bit vector, arrays, and records

Bit_vector Type

The bit_vector type represents an array of bits; each element of the array is a single bit. The following example illustrates the implementation of type bit_vector:

Port (I1 : in bit; I2 : in bit_vector (5 downto 0); Sum : out bit);

In the above statement, port I2 is declared as type bit_vector; it has six bits.

b. Array Type

This type is declared by using the predefined word array. For example, the following statements declare the variable memory to be a single dimensional array of eight elements, and each element is an integer:

subtype wordN is integer;

type intg is array (7 downto 0) of wordN;

...........

variable memory : intg;

Arrays can also be multidimensional.

c. Record Type

An object of record type is composed of elements of the same or different types. An example of record type is shown below:

Type forecast is

record

Tempr : integer range -100 to 100;

Day : real;

Cond : bit;

end record;

............

variable temp : forecast

Variable temp is of type forecast; type forecast includes record, and record has three different types: integer, real, and bit.

3. Access Types

Values belonging to an access type are pointers to objects of other types. For example:

type ptr_weathr is access forecast;

The type ptr_weathr is a pointer to the type forecast shown in last example

4. File Types

Objects of type file can be read from and written to using built-in functions and procedures that are provided in the standard library. Some of these procedures and functions are file_open to open files, readline to read a line from the file, writeline to write a line into the file, and file_close to close the file.

5. Other Types

There are several other types provided by external libraries. For example, the IEEE library contains a package by the name of std_logic_1164. This package contains an extremely important type: std_logic.

Std_Logic Type

Std_Logic has nine values, including 1 and 0. Package std_logic_1164 should be attached to the VHDL module.

Value	Definition
U	Uninitialized
X	Unknown
0	Low
1	High
Z	High Impedance
W	Weak unknown
L	Weak low
H	Weak high
-	Don’t care

b. Std_logi c_vector Type

The type std_logic_vector represents an array. Each element of the array is a single bit of type std_logic.

Example:

Port (I1 : in bit; I2 : in std_logic_vector (5 downto 0);

Sum : out bit);

In the above statement, port I2 is declared as type std_logic_vector; it has six bits.

c. Signed

Signed is a numeric type. It is declared in the external package numeric_std and represents signed integer data in the form of an array. The leftmost bit is the sign; objects of type signed are represented in 2’s complement form. Consider the statement:

Variable prod : signed (3 downto 0) := 1010;

The above statement declares the variable prod. It is of type signed, has four bits, and its initial value is 1010, or –6 (in decimal).

d. Unsigned

The type unsigned represents unsigned integer data in the form of an array of std_logic and is a part of the package numeric_std.

Variable Qout : unsigned (3 downto 0) := 1010;

The above statement declares variable Qout as of type unsigned, it has

four bits, and its initial value is 1010, or 10 (in decimal).

Q12) Explain all data types used in Verilog. A12) Verilog supports several data types including nets, registers, vectors, integer, real, parameters, and arrays.

Nets

Nets are declared by the predefined word wire. Nets have values that change continuously by the circuits that are driving them. Verilog supports four values for nets.

Value	Definition
0	Logic 0 (False)
1	Logic 1 (True)
X	Unknown
Z	High Impedance

Example:

wire sum;

wire S1 = 1’b0;

The first statement declares a net by the name sum. The second statement declares a net by the name of S1; its initial value is 1’b0, which represents 1 bit with value 0.

2. Register

Register, in contrast to nets, stores values until they are updated. Register, as its name suggests, represents data-storage elements. Register is declared by the predefined word reg. Verilog supports four values for register.

Value	Definition
0	Logic 0 (False)
1	Logic 1 (True)
X	Unknown
Z	High Impedance

3. Vectors

Vectors are multiple bits. A register or a net can be declared as a vector. Vectors are declared by brackets [ ]. Examples of vectors are:

wire [3:0] a = 4’b1010;

reg [7:0] total = 8’d12;

The first statement declares a net a. It has four bits, and its initial value

is 1010 (b stands for bit). The second statement declares a register total.Its size is eight bits, and its value is decimal 12 (d stands for decimal).

4. Integers

Integers are declared by the predefined word integer. An example of

integer declaration is:

integer no_bits;

5. Real

Real (floating-point) numbers are declared with the predefined word real. Examples of real values are 2.4, 56.3, and 5e12. The value 5e12 is

equal to 5 × 1012. The following statement declares the register weight as real:

real weight;

6. Parameter

Parameter represents a global constant. It is declared by the predefined word parameter. The following is an example of implementing parameters:

module compr_genr (X, Y, xgty, xlty, xeqy);

parameter N = 3;

input [N:0] X, Y;

output xgty, xlty, xeqy;

wire [N:0] sum, Yb;

To change the size of the inputs x and y, the size of the nets sum, and

the size of net Yb to eight bits, the value of N is changed to seven as:

parameter N = 7

7. Arrays

Verilog, in contrast to VHDL, does not have a predefined word for array. Registers and integers can be written as arrays. Consider the following statements:

parameter N = 4;

parameter M = 3;

reg signed [M:0] carry [0:N];

The above statements declare an array by the name carry. The array carry has five elements, and each element is four bits. The four bits are in two’s complement form. For example, if the value of a certain element is 1001, then it is equivalent to decimal –7.

Q13) List all the steps of simulation and synthesisA13) The steps of simulation and synthesis in general can be summarized as follows:

Choose the preferred language to describe the system. The language may be VHDL, Verilog, or mixed-language (both VHDL and Verilog).

Choose the style or type of description.

Write the code. If writing a VHDL module, be sure to attach all the necessary packages and libraries. At this step, some HDL packages require the user to select the type of synthesis technology and chip type before compilation.

Compile the code using the compiler supplied by the HDL package. The compiler checks that the code satisfies the rules of the language and displays any errors. Some compilers suggest how to fix the errors.

After successful compilation, the code is tested to see that it correctly describes the system. This test is done by selecting the input and output signals to be tested. For example, if a 2 x 1 multiplexer is being described, the two inputs, the select line, and the output might be selected. The way these signals are selected differs from one simulator to the other; there might be different ways to select signals even within the same simulator. Some simulators are graphical. All signals in the system are displayed in graphical fashion; the user selects the signals and assigns initial values for them. The user then clicks a button to run the simulation, and a simulation screen appears showing the waveform of the selected signals. Some other simulators allow the user to write HDL code, called test bench, for testing the source code.

After the simulation verifies that the signals behave as expected, the compiled code can be synthesized. The simulator CAD package usually has a synthesizer. The synthesizer converts the compiled code into a schematic and generates a net list. The net list can be downloaded onto a chip, usually field-programmable gate arrays.

Q14) Differentiate between VHDL and VerilogA14)

Parameter	VHDL	Verilog
Data types	VHDL types are built in or users can create and define them. User-defined types give the user a tool to write the code effectively;	Compared to VHDL, Verilog data types are very simple and easy to use. All types are defined by the language.
Ease of learning	For beginners, VHDL may seem hard to learn because of its rigid type requirements.	Easy to learn, Verilog users just write the module without worrying about what library or package should be attached.
Libraries and Packages	Libraries and packages can be easily attached to the standard VHDL package. Packages can include procedures and functions, and the package can be made available to any module that needs to use it.	Libraries are not as easily implemented as in VHDL, however the basic Verilog package includes several libraries as integral part of the package.
Base Language	VHDL is based on Ada and Pascal languages.	Verilog is based on C language
Case Sensitivity	Case Insensitive	Case Sensitive

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