Bihar Engineering University, Bihar, Electrical & Electronics Engineering Semester 6, Introduction to VLSI Design Syllabus

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Unit - 2 Combinational MOS Logic Circuits

2.1 Circuit Families Static CMOS

2.2 Ratioed Circuits

2.3 Cascode Voltage Switch Logic

2.4 Dynamic Circuits

2.5 Pass Transistor Logic

2.6 Transmission Gates

2.7 Domino

2.8 Dual Rail Domino

2.9 CPL

2.10 DCVSPG

2.11 DPL

2.12 Circuit Pitfalls

2.13 Power Dynamic Power Static Power

2.14 Low Power Architecture

Unit - 3 SEQUENTIAL CIRCUIT DESIGN

Unit 3

SEQUENTIAL CIRCUIT DESIGN

3.1 Static latches and Registers

3.2 Dynamic latches and Registers

3.3 Pulse Registers

3.4 Sense Amplifier Based Register

3.5 Pipelining

3.6 Schmitt Trigger

3.7 Monostable Sequential Circuits

3.8 Astable Sequential Circuits

3.9 Timing Issues Timing

3.10 Classification of Digital System

3.11 Synchronous Design

Unit - 4 DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

Unit 4

DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

4.1 Arithmetic Building Blocks Data Paths

4.2 Adders

4.3 Multipliers

4.4 Shifters

4.5 ALUs

4.6 Power and speed tradeoffs

4.7 Case Study Design as a tradeoff

4.8 Designing Memory and Array structures Memory Architectures and Building Blocks

4.9 Memory Core

4.10 Memory Peripheral Circuitry

Unit - 5 IMPLEMENTATION STRATEGIES AND TESTING

Unit 5

IMPLEMENTATION STRATEGIES AND TESTING

5.1 FPGA Building Block Architectures

5.2 FPGA Interconnect Routing Procedures

5.3 Design for Testability Ad Hoc Testing

5.4 Scan Design

5.5 BIST

5.6 IDDQ Testing

5.7 Design for Manufacturability

5.8 Boundary Scan

Unit 1 - Introduction to MOS Transistor

1.1 MOS Transistor

1.2 CMOS logic

1.3 Inverter

1.4 Pass Transistor

1.5 Transmission gate

1.6 Layout Design Rules

1.7 Gate Layouts

1.8 Stick Diagrams

1.9 LongChannel IV Characteristics

1.10 CV Characteristics

1.11 Non ideal IV Effects

1.12 DC Transfer characteristics

1.13 RC Delay Model

1.14 Elmore Delay

1.15 Linear Delay Model

1.16 Logical effort

1.17 Parasitic Delay

1.18 Delay in Logic Gate

1.19 Scaling

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Other Subjects of Semester-2-
Digital signal processing
Speech and audio processing
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