Bihar Engineering University, Bihar, Information Technology Semester 4, Computer Organization & Architecture Syllabus

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Unit - 1 Functional blocks of a computer, Data representation

1.1 CPU memory inputoutput subsystems control unit

1.2 Instruction set architecture of CPU–registers

1.3 Instruction execution cycle

1.4 RTL interpretation of instructions

1.5 Addressing modes

1.6 Instruction set

1.7 Case study – instruction sets of some common CPUs

1.8 Signed number representation

1.9 Fixed and floatingpoint representations

1.10 Character representation

1.11 Computer arithmetic – integer addition and subtraction

1.12 Ripple carry adder

1.13 Carry lookahead adder

1.14 Multiplication – shiftandadd Booth multiplier carry save multiplier

1.15 Division restoring and nonrestoring techniques

1.16 Floating point arithmetic

Unit - 2 Introduction to x86 architecture CPU control unit design, Peripheral devices and their characteristics

2.1 Hardwired and microprogrammed design approaches

2.2 Case study – design of a simple hypothetical CPU

2.3 Memory system design semiconductor memory technologies memory organization

2.4 Inputoutput subsystems

2.5 IO device interface Interrupt driven and DMA

2.6 IO transfers–program controlled

2.7 Privileged and nonprivileged instructions

2.8 Software interrupts and exceptions

2.9 Programs and processes–role of interrupts in process state transitions

2.10 IO device interfaces – SCII USB

Unit - 3 Pipelining, Parallel Processors

3.1 Basic concepts of pipelining

3.2 Throughput and speedup

3.3 Pipeline hazards

3.4 Introduction to parallel processors

3.5 Concurrent access to memory and cache coherency

Unit - 4 Memory organization

4.1 Memory interleaving

4.2 Concept of hierarchical memory organization

4.3 Cache memory cache size vs. Block size

4.4 Mapping functions

4.5 Replacement algorithms

4.6 Write policies

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Other Subjects of Semester-2
Machine learning
Database management system
Formal language & automata theory
Management i (organizational behaviour)
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