Dr A.P.J. Abdul Kalam Technical University, UP (AKTU), Electronics and Communication engineering Semester 7, VLSI Design Syllabus

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Unit - 1 Introduction

Unit 1

Introduction

1.1 A Brief History

1.3 Preview

1.3 MOS Transistor

1.4 CMOS logic

1.5 CMOS Fabrication and Layout

1.6 Design Partitioning

1.7 Logic Design

1.8 Circuit Design

1.9 Physical Design

1.10 Design Verification

1.11 Fabrication

1.12 Packaging and Testing

Unit - 2 Delay

Unit 2

Delay

2.1 Introduction

2.2 Transient Response

2.3 RC Delay Model

2.4 Linear Delay Model

2.5 Logical effort of Paths

2.6 Timing Analysis Delay Models

2.7 Power Introduction

2.8 Dynamic Power and Static Power

Unit - 3 Energy

Unit 3

Energy – Delay Optimization

3.1 Energy – Delay Optimization

3.2 Low Power Architectures

3.3 Interconnect Introduction

3.4 Interconnect Modelling

3.5 Interconnect Impact

3.6 Interconnect Engineering

3.7 Logical Effort with Wires

Unit - 4 Dynamic Logic Circuits

Unit 4

Dynamic logic circuits

4.1 Dynamic logic circuits Introduction

4.2 Basic principle of pass transistor circuits

4.3 Synchronous dynamic circuit techniques

4.4 Dynamic CMOS circuit techniques

4.5 Domino CMOS logic

4.6 Semiconductor memories Introduction

4.7 DRAM

4.8 SRAM

4.9 ROM

4.10 Flash memory

Unit - 5 Low – Power CMOS Logic Circuits

Unit 5

Low – Power CMOS Logic Circuits

5.1 Low – Power CMOS Logic Circuits Introduction

5.2 Overview of Power Consumption

5.3 Low – Power Design through voltage scaling

5.4 Estimation and Optimization of switching activity

5.5 Reduction of Switched Capacitance and Adiabatic Logic Circuits

5.6 Design for Testability Introduction

5.7 Fault Types and Models

5.8 Controllability and Observability

5.9 Ad Hoc Testable Design Techniques

5.10 Scan Based

5.11 BIST Technique

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Other Subjects of 1
Data communication networks
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