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Jharkhand University of Technology, Jharkhand
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Computer Organization and Architecture
Jharkhand University of Technology, Jharkhand, Computer Engineering Semester 5, Computer Organization and Architecture Syllabus
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Unit - 1 Basics Of Digital Electronics
Unit 1
Basics of Digital Electronics
1.1 Basics of Digital Electronics Multiplexers
1.2 De multiplexers
1.3 Decoder
1.4 Encoder
1.5 Codes
1.6 Logic gates
1.7 Flip flops
1.8 Registers
1.9 Register Transfer and Micro Operations Bus and Memory Transfer
1.10 Logic Micro Operations
1.11 Shift Micro Operations
1.12 Register transfer and register transfer language
1.13 Design of arithmetic logic unit
Unit - 2 Basic Computer Organization
Unit 2
Basic Computer Organization
2.1 Instruction codes
2.2 Computer instructions
2.3 Timing and Control
2.4 Instruction cycle
2.5 Memory reference Instruction
2.6 Complete computer description
2.7 Design of basic computer
2.8 Input output
2.9 Interrupt
Unit - 3 Control Unit
Unit 3
Control Unit and Central Processing Unit
3.1 Control Unit Hardwired controls
3.2 Micro programmed controls
3.3 Central Processing Unit Program control
3.4 Reduced instruction set computer
3.5 Complex instruction set
3.6 Computer
3.7 Data Transfer
3.8 Manipulation
3.9 General register
3.10 Stack organization
3.11 Addressing mode
Unit - 4 Computer Arithmetic
Unit 4
Computer Arithmetic
4.1 Addition and subtraction algorithm
4.2 Multiplication algorithm
4.3 Division algorithms
Unit - 5 Input-Output Organization
Unit 5
InputOutput Organization and Memory Unit
5.1 Priority interrupt
5.2 Peripheral devices
5.3 Input output interface
5.4 Data transfer schemes
5.5 Program control
5.6 Interrupts
5.7 Direct memory access transfer
5.8 Inputoutput processor
5.9 Memory Unit High speed memories
5.10 Memory hierarchy
5.11 Processor Vs Memory speed
5.12 Cache memory
5.13 Associative memory
5.14 Inter leave
5.15 Virtual memory
5.16 Memory management
Unit - 6 Introduction To Parallel Processing
Unit 6
Introduction to Parallel Processing
6.1 Pipelining
6.2 Characteristics of multiprocessors
6.3 Interconnection structures
6.4 Inter processor arbitration
6.5 Inter processor communication
6.6 Synchronization
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Other Subjects of Semester-1
Compiler design
Computer graphics
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