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Jharkhand University of Technology, Jharkhand, Electrical Engineering Semester 4, Digital Electronics And Logic Design Syllabus
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Unit - 1 Binary Codes And Boolean Algebra
Unit 1
Binary Codes and Boolean algebra
1.1 Analog and Digital
1.2 Binary Number System
1.3 Addition of binary numbers
1.4 Subtraction of binary numbers
1.5 Multiplication of binary numbers
1.6 Division of binary numbers
1.7 Subtraction using 2’s complement method
1.8 Binary codes weighted and nonweighted codes
1.9 Self complementary codes
1.10 BCD
1.11 Excess3
1.12 Gray codes
1.13 Alphanumeric codes
1.14 ASCII Codes
1.15 Boolean algebra
1.16 Boolean Laws and Expression using Logic Gates
1.17 Realization of different gates using Universal gates
1.18 De Morgan’s Theorem
1.19 Duality Theorems
Binary Codes and Boolean algebra
Unit 1
Binary Codes and Boolean algebra
1.1 Analog and Digital
1.2 Binary Number System
Unit 1
Binary Codes and Boolean algebra
1.1 Analog and Digital
1.2 Binary Number System
1.3 Addition of binary numbers
1.4 Subtraction of binary numbers
1.5 Multiplication of binary numbers
1.6 Division of binary numbers
1.7 Subtraction using 2’s complement method
1.8 Binary codes weighted and nonweighted codes
1.9 Self complementary codes
1.10 BCD
1.11 Excess3
1.12 Gray codes
1.13 Alphanumeric codes
1.14 ASCII Codes
1.15 Boolean algebra
1.16 Boolean Laws and Expression using Logic Gates
1.17 Realization of different gates using Universal gates
1.18 De Morgan’s Theorem
1.19 Duality Theorems
Unit - 2 Boolean Function Minimization Techniques
Unit 2
Boolean function minimization Techniques
2.1 Standard forms SOP POS
2.2 Simplification of Switching function representation Maxterm Minterm
2.3 Boolean expression representation using logic gates
2.4 Propagation delay in logic gate
2.5 Karnaugh map Kmapup to 5 variables
2.6 Mapping and minimization of SOP and POS expression
2.7 Don’t care condition
2.8 Conversion from SOP to POS and POS to SOP form using Kmap
2.9 Quine Mccluskey method minimization technique
2.10 Prime implicant table
Unit 2
Boolean function minimization Techniques
2.1 Standard forms SOP POS
Unit 2
Boolean function minimization Techniques
2.1 Standard forms SOP POS
Unit 2
Boolean function minimization Techniques
2.1 Standard forms SOP POS
2.2 Simplification of Switching function representation Maxterm Minterm
2.3 Boolean expression representation using logic gates
2.4 Propagation delay in logic gate
2.5 Karnaugh map Kmapup to 5 variables
2.6 Mapping and minimization of SOP and POS expression
2.7 Don’t care condition
2.8 Conversion from SOP to POS and POS to SOP form using Kmap
2.9 Quine Mccluskey method minimization technique
2.10 Prime implicant table
Unit - 3 Combinational Circuits Design
Unit 3
Combinational Circuits Design
3.1 Adder Half and Full
3.2 Subtractor Half and Full
3.3 Parallel Binary adder
3.4 BCD Adder
3.5 Binary multipliers
3.6 Code Converters
3.7 Parity bit generator
3.8 Comparators
3.9 Decoder
3.10 BCD to 7segment Decoder
3.11 Encoders
3.12 Priority Encoders
3.13 Multiplexers
3.14 De Multiplexers
Sequential Circuits Elements
Unit 3
Combinational Circuits Design
4.1 Introduction to sequential circuit
Unit 3
Combinational Circuits Design
Unit 3
Combinational Circuits Design
3.1 Adder Half and Full
3.2 Subtractor Half and Full
3.3 Parallel Binary adder
3.4 BCD Adder
3.5 Binary multipliers
3.6 Code Converters
3.7 Parity bit generator
3.8 Comparators
3.9 Decoder
3.10 BCD to 7segment Decoder
3.11 Encoders
3.12 Priority Encoders
3.13 Multiplexers
3.14 De Multiplexers
Unit - 4 Sequential Circuits Elements
Unit 4
Sequential Circuits Elements
4.1 Introduction to sequential circuit
4.2 Flipflop Timing Circuits SR latch Gated latch Tri state logic
4.3 Edge triggered flipplop D JK T Flipflop flipflop asynchronous inputs characteristic and excitation table of Flipflop
4.4 Master slave JK flip flop
4.5 Inter conversion of Flipflop
4.6 Study of timing parameters of flipflop
4.3 Shift registers
4.4 Buffer register
4.5 Controlled buffer register
4.6 Data transmission in shift resistor
4.7 SISO
4.8 SIPO
4.9 PISO
4.10 PIPO
4.11 Bidirectional shift register
4.12 Universal shift register
4.13 Counter Classification
4.14 Ripple or asynchronous counter
4.15 Effect of propagation delay in ripple counters
4.16 Updown counter
4.17 Design of Modn counter
4.18 Synchronous counter
4.19 Ring counter
4.20 Johnson counter
4.21 Introduction to FSM Design of synchronous FSM
4.22 Algorithmic State Machines charts
Unit 4
Sequential Circuits Elements
Unit 4
Sequential Circuits Elements
4.1 Introduction to sequential circuit
4.2 Flipflop Timing Circuits SR latch Gated latch Tri state logic
4.3 Edge triggered flipplop D JK T Flipflop flipflop asynchronous inputs characteristic and excitation table of Flipflop
4.4 Master slave JK flip flop
4.5 Inter conversion of Flipflop
4.6 Study of timing parameters of flipflop
4.3 Shift registers
4.4 Buffer register
4.5 Controlled buffer register
4.6 Data transmission in shift resistor
4.7 SISO
4.8 SIPO
4.9 PISO
4.10 PIPO
4.11 Bidirectional shift register
4.12 Universal shift register
4.13 Counter Classification
4.14 Ripple or asynchronous counter
4.15 Effect of propagation delay in ripple counters
4.16 Updown counter
4.17 Design of Modn counter
4.18 Synchronous counter
4.19 Ring counter
4.20 Johnson counter
4.21 Introduction to FSM Design of synchronous FSM
4.22 Algorithmic State Machines charts
Unit - 5 Logic Families And VLSI Design Flow
Unit 5
Logic Families and VLSI Design flow
5.1 Logic Families and Semiconductor Memories TTL NAND gate
5.2 Specifications
5.3 Noise margin
5.4 Propagation delay
5.5 Fanin
5.6 Fanout
5.7 TTL
5.8 ECL
5.9 CMOS families and their interfacing
5.10 Memory elements
5.11 Concept of Programmable logic devices like FPGA
5.12 Logic implementation using Programmable Devices VLSI Design flow Design entry
5.13 Schematic
5.14 FSM HDL
5.15 Different modeling styles in VHDL
5.16 Data types and objects
5.17 Dataflow
5.18 Behavioral and Structural Modeling
5.19 Synthesis and Simulation VHDL constructs and codes for combinational and sequential circuits
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