Other university, Electrical & Electronics Engineering , Introduction to VLSI Design Syllabus

Introduction to VLSI Design Lecture notes | Videos | Free pdf Download | Previous years solved question papers | MCQs | Question Banks| Syllabus
Get access to 100s of MCQs, Question banks, notes and videos as per your syllabus.
Try Now for free

Unit - 1 Introduction To MOS Transistor

Unit 1

INTRODUCTION TO MOS TRANSISTOR

1.1 MOS Transistor

1.2 CMOS logic

1.3 Inverter

1.4 Pass Transistor

1.5 Transmission gate

1.6 Layout Design Rules

1.7 Gate Layouts

1.8 Stick Diagrams

1.9 LongChannel IV Characteristics

1.10 CV Characteristics

1.11 Non ideal IV Effects

1.12 DC Transfer characteristics

1.13 RC Delay Model

1.14 Elmore Delay

1.15 Linear Delay Model

1.16 Logical effort

1.17 Parasitic Delay

1.18 Delay in Logic Gate

1.19 Scaling

Unit - 2 Combinational MOS Logic Circuits

Unit 2

COMBINATIONAL MOS LOGIC CIRCUITS

2.1 Circuit Families Static CMOS

2.2 Ratioed Circuits

2.3 Cascode Voltage Switch Logic

2.4 Dynamic Circuits

2.5 Pass Transistor Logic

2.6 Transmission Gates

2.7 Domino

2.8 Dual Rail Domino

2.9 CPL

2.10 DCVSPG

2.11 DPL

2.12 Circuit Pitfalls

2.13 Power Dynamic Power Static Power

2.14 Low Power Architecture

Unit - 3 Sequential Circuit Design

Unit 3

SEQUENTIAL CIRCUIT DESIGN

3.1 Static latches and Registers

3.2 Dynamic latches and Registers

3.3 Pulse Registers

3.4 Sense Amplifier Based Register

3.5 Pipelining

3.6 Schmitt Trigger

3.7 Monostable Sequential Circuits

3.8 Astable Sequential Circuits

3.9 Timing Issues Timing

3.10 Classification of Digital System

3.11 Synchronous Design

Unit - 4 Design Of Arithmetic Building Blocks And Subsystem

Unit 4

DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM

4.1 Arithmetic Building Blocks Data Paths

4.2 Adders

4.3 Multipliers

4.4 Shifters

4.5 ALUs

4.6 Power and speed tradeoffs

4.7 Case Study Design as a tradeoff

4.8 Designing Memory and Array structures Memory Architectures and Building Blocks

4.9 Memory Core

4.10 Memory Peripheral Circuitry

Unit - 5 Implementation Strategies And Testing

Unit 5

IMPLEMENTATION STRATEGIES AND TESTING

5.1 FPGA Building Block Architectures

5.2 FPGA Interconnect Routing Procedures

5.3 Design for Testability Ad Hoc Testing

5.4 Scan Design

5.5 BIST

5.6 IDDQ Testing

5.7 Design for Manufacturability

5.8 Boundary Scan

Download EEE Third Year syllabus pdf
Get access to 100s of MCQs, Question banks, notes and videos as per your syllabus.
Try Now for free
Other Subjects of third-year
Power system-i
Control systems
Power electronics
Power system - ii
Integrated circuits
Digital signal processing
Analog & digital communication system
Popular posts
Top 10 ECE colleges in India
What is race around condition
What are programmable logic gates
Share  
Link Copied
More than 1 Million students use Goseeko! Join them to feel the power of smart learning.
Spot anything incorrect? Contact us