Rashtrasant Tukadoji Maharaj Nagpur University, Maharashtra, Artificial Intelligence Semester 3, Computer Architecture & Organization Syllabus

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Unit - 1 Functional blocks of a computer

Unit 1

Functional blocks of a computer

1.1 CPU memory inputoutput subsystems control unit

1.2 Instruction set architecture of CPU–registers

1.3 Instruction execution cycle

1.4 Addressing modes

Unit - 2 Data representation

Unit 2

Data representation

2.1 Fixed and floatingpoint representations

2.2 Computer arithmetic – integer addition and subtraction

2.3 Carry lookahead adder

2.4 Multiplication – shiftandadd Booth multiplier

2.5 Division restoring and nonrestoring techniques

Unit - 3 CPU control unit design

Unit 3

CPU control unit design

3.1 Hardwired and microprogrammed design approaches

3.2 Memory system design semiconductor memory technologies memory organization

Unit - 4 Peripheral devices and their characteristics

Unit 4

Peripheral devices and their characteristics

4.1 Inputoutput subsystems

4.2 IO device interface Interrupt driven and DMA

4.3 IO transfers–programcontrolled

4.4 Software interrupts and exceptions

4.5 IO device interfaces –USB

4.6 Memory organization Memory interleaving

4.7 Concept of hierarchical memory organization

4.8 Cache memory cache size vs. Block size

4.9 Mapping functions

4.10 Replacement algorithms

4.11 Write policies

Unit - 5 Parallel Processors and Pipelining

Unit 5

Parallel Processors and Pipelining

5.1 Parallel Processors Introduction to parallel processors

5.2 Concurrent access to memory and cache coherency

5.3 Pipelining Basic concepts of pipelining

5.4 Throughput and speedup

5.5 Pipeline hazards

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Other Subjects of Semester-3
Data structures
Operating systems
Digital circuits & microprocessor
Discrete mathematics and graph theory
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