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Visvesvaraya Technological University, Karnataka
Computer Engineering
Computer Organization
Visvesvaraya Technological University, Karnataka, Computer Engineering Semester 4, Computer Organization Syllabus
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Unit - 1 Basic Structure of Computers
1.1 Basic Structure of Computers Computer Types Functional Units
1.2 Basic Operational Concepts
1.3 Bus Structures
1.4 Performance – Processor Clock Basic Performance Equation
1.5 Clock Rate
1.6 Performance Measurement
1.7 Historical Perspective
1.8 Machine Instructions and Programs Numbers Arithmetic Operations and Characters
1.9 Memory Location and Addresses
1.10 Memory Operations
1.11 Instructions and Instruction Sequencing
Unit - 2 Machine Instructions and Programs
2.1 Machine Instructions and Programs contd. Addressing Modes
2.2 Assembly Language
2.3 Basic Input and Output Operations
2.4 Stacks and Queues
2.5 Subroutines
2.6 Additional Instructions
2.7 Encoding of Machine Instructions
Unit - 3 Input-Output Organization
3.1 Inputoutput Organization Accessing IO Devices
3.2 Interrupts – Interrupt Hardware
3.3 Enabling and Disabling Interrupts
3.4 Handling Multiple Devices
3.5 Controlling Device Requests
3.6 Exceptions
3.7 Direct Memory Access
3.8 Buses
Unit - 4 Input-Output Organization
4.1 Inputoutput Organization contd. Interface Circuits
4.2 Standard IO Interfaces – PCI Bus SCSI Bus USB
Unit - 5 Memory System
5.1 Memory System Basic Concepts
5.2 Semiconductor RAM Memories
5.3 Read Only Memories
5.4 Speed Size and Cost
5.5 Cache Memories – Mapping Functions
5.6 Replacement Algorithms
5.7 Performance Considerations
5.8 Virtual Memories
5.9 Secondary Storage
Unit - 6 Arithmetic
6.1 Arithmetic Addition and Subtraction of Signed Numbers
6.2 Design of Fast Adders
6.3 Multiplication of Positive Numbers
6.4 Signed Operand Multiplication
6.5 Fast Multiplication
6.6 Integer Division
6.7 Floatingpoint Numbers and Operations
Unit - 7 Basic Processing Unit
7.1 Basic Processing Unit Some Fundamental Concepts
7.2 Execution of a Complete Instruction
7.3 Multiple Bus Organization
7.4 Hardwired Control Microprogrammed Control
Unit - 8 Multicores, Multiprocessors, and Clusters
8.1 Multicores Multiprocessors and Clusters Performance
8.2 The Power Wall
8.3 The Switch from Uniprocessors to Multiprocessors
8.4 Amdahl’s Law
8.5 Shared Memory Multiprocessors
8.6 Clusters and other Message Passing Multiprocessors
8.7 Hardware Multithreading
8.8 SISD IMD SIMD SPMD and Vector
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Other Subjects of Semester-2
Microprocessors
Unix and shell programming
Engineering mathematics - iv
Graph theory and combinatorics
Design and analysis of algorithms
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