Visvesvaraya Technological University, Karnataka, Electronics and Communication engineering Semester 4, Fundamentals of HDL Syllabus

Fundamentals of HDL Lecture notes | Videos | Free pdf Download | Previous years solved question papers | MCQs | Question Banks| Syllabus
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Unit - 1 Introduction

1.1 Why HDL

1.2 A Brief History of HDL

1.3 Structure of HDL module

1.4 Types of Description

1.5 Ports

1.6 Operators

1.7 Data Types

1.8 Simulation and Synthesis

1.9 Brief Comparison between VHDL and Verilog

Unit - 2 Data Flow Descriptions

2.1 Highlights of DataFlow Descriptions

2.2 Structure of DataFlow Description

2.3 Examples of Dataflow description

2.4 Data Type Vector

Unit - 3 Behavioural Descriptions

3.1 Behavioral Description highlights

3.2 Structure of HDL Behavioral Description

3.3 The VHDL Variable assignment statement

3.4 Sequential statements in VHDL

Unit - 4 Structural Descriptions

4.1 Highlights of structural Description

4.2 Organization of the structural Description

4.3 Binding

4.4 State Machines

4.5 Generate Generic and Parameter

Unit - 5 Procedures, Task and Functions

5.1 Highlights of Procedures tasks and Functions

5.2 Procedures and tasks

5.3 Functions

5.4 File Processing

5.5 File Processing Examples

Unit - 6 Mixed Type Descriptions

6.1 Why MixedType Description

6.2 VHDL User Defined Types

6.3 VHDL Packages

6.4 Mixed type Description Examples

Unit - 7 Mixed Language Descriptions

7.1 Highlights of MixedLanguage Description

7.2 How to invoke one language from the other

7.3 Mixed Language Description Example

7.4 Limitations of Mixed Language Description

Unit - 8 Synthesis Basics

8.1 Highlights of Synthesis

8.2 Synthesis information from Entity and Module

8.3 Mapping Process and Always in the Hardware Domain

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Other Subjects of Semester-2
Control systems
Microcontrollers
Signals & systems
Linear ics & applications
Engineering mathematics - iv
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