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VLSI Design & Technology (404181)

Unit I: VHDL Modeling

Data objects, Data types, Entity, Architecture & types of modeling, Sequential statements, Concurrent statements, Packages, Sub programs, Attributes, VHDL Test bench, Test benches using text files. VHDL modeling of Combinational, Sequential logics & FSM, Meta-stability.

Unit II: PLD Architectures

PROM, PLA, PAL: Architectures and applications. Software Design Flow. CPLD Architecture, Features, Specifications, Applications. FPGA Architecture, Features, Specifications, Applications.

Unit III: SoC& Interconnect

Clock skew, Clock distribution techniques, clock jitter. Supply and ground bounce, power distribution techniques. Power optimization. Interconnect routing techniques; wire parasitic, Signal integrity issues. I/O architecture, pad design. Architectures for low power.

Unit IV: Digital CMOS Circuits

MOS Capacitor, MOS Transistor theory, C-V characteristics, Non ideal I-V effects, Technology Scaling. CMOS inverters, DC transfer characteristics, Power components, Power delay product. Transmission gate. CMOS combo logic design. Delays: RC delay model, Effective resistance, Gate and diffusion capacitance, Equivalent RC circuits; Linear delay model, Logical effort, Parasitic delay, Delay in a logic gate, Path logical efforts.

Unit V: Analog CMOS Design

Current sink and source, Current mirror. Active load, Current source and Push-pull inverters. Common source, Common drain, Common gate amplifiers. Cascode amplifier, Differential amplifier, Operational amplifier.

Unit VI: Testability6L

Types of fault, Need of Design for Testability (DFT), Testability, Fault models, Path sensitizing, Sequential circuit test, BIST, Test pattern generation, JTAG & Boundary scan, TAP Controller.

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